loadpatents
name:-0.019541025161743
name:-0.015714883804321
name:-0.0097541809082031
Wilkerson; Brett P. Patent Filings

Wilkerson; Brett P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wilkerson; Brett P..The latest application filed is for "optical die-last wafer-level fanout package with fiber attach capability".

Company Profile
12.17.23
  • Wilkerson; Brett P. - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Offset-aligned three-dimensional integrated circuit
Grant 11,437,359 - Wilkerson , et al. September 6, 2
2022-09-06
Optical Die-last Wafer-level Fanout Package With Fiber Attach Capability
App 20220206221 - RAVICHANDRAN; SIDDHARTH ;   et al.
2022-06-30
Structural Thermal Interfacing For Lidded Semiconductor Packages
App 20220199429 - SHAH; PRIYAL ;   et al.
2022-06-23
Molded chip package with anchor structures
Grant 11,367,628 - Shah , et al. June 21, 2
2022-06-21
Arrangement And Thermal Management Of 3d Stacked Dies
App 20220059425 - WUU; JOHN ;   et al.
2022-02-24
Hybrid Bonded Interconnect Bridging
App 20220052023 - FU; LEI ;   et al.
2022-02-17
Mixed Density Interconnect Architectures Using Hybrid Fan-out
App 20220051989 - AGARWAL; RAHUL ;   et al.
2022-02-17
Arrangement and thermal management of 3D stacked dies
Grant 11,189,540 - Wuu , et al. November 30, 2
2021-11-30
Arrangement and thermal management of 3D stacked dies
Grant 11,164,807 - Wuu , et al. November 2, 2
2021-11-02
Scheme For Enabling Die Reuse In 3d Stacked Products
App 20210098441 - Wuu; John J. ;   et al.
2021-04-01
Fan-out Package With Reinforcing Rivets
App 20210057352 - Agarwal; Rahul ;   et al.
2021-02-25
Molded Chip Package With Anchor Structures
App 20210020459 - Shah; Priyal ;   et al.
2021-01-21
Offset-aligned Three-dimensional Integrated Circuit
App 20200194413 - Wilkerson; Brett P. ;   et al.
2020-06-18
Offset-aligned three-dimensional integrated circuit
Grant 10,573,630 - Wilkerson , et al. Feb
2020-02-25
Arrangement And Thermal Management Of 3d Stacked Dies
App 20190393123 - Wuu; John ;   et al.
2019-12-26
Arrangement And Thermal Management Of 3d Stacked Dies
App 20190393124 - Wuu; John ;   et al.
2019-12-26
Offset-aligned Three-dimensional Integrated Circuit
App 20190326272 - Wilkerson; Brett P. ;   et al.
2019-10-24
Arrangement and thermal management of 3D stacked dies
Grant 10,431,517 - Wuu , et al. O
2019-10-01
Stacked Dies And Dummy Components For Improved Thermal Performance
App 20190189590 - Agarwal; Rahul ;   et al.
2019-06-20
Stacked dies and dummy components for improved thermal performance
Grant 10,312,221 - Agarwal , et al.
2019-06-04
Arrangement And Thermal Management Of 3d Stacked Dies
App 20190067152 - Wuu; John ;   et al.
2019-02-28
Semiconductor devices with compliant interconnects
Grant 9,324,667 - Uehling , et al. April 26, 2
2016-04-26
Packaged integrated circuit having large solder pads and method for forming
Grant 8,766,453 - Uehling , et al. July 1, 2
2014-07-01
Packaged Integrated Circuit Having Large Solder Pads And Method For Forming
App 20140117554 - Uehling; Trent S. ;   et al.
2014-05-01
Semiconductor package structure having an air gap and method for forming
Grant 8,704,370 - Uehling , et al. April 22, 2
2014-04-22
Semiconductor Package Structure Having An Air Gap And Method For Forming
App 20140001632 - Uehling; Trent S. ;   et al.
2014-01-02
Semiconductor Devices With Compliant Interconnects
App 20130181340 - UEHLING; Trent S. ;   et al.
2013-07-18
Die level metal density gradient for improved flip chip package reliability
Grant 7,276,435 - Pozder , et al. October 2, 2
2007-10-02
Integrated circuit having structural support for a flip-chip interconnect pad and method therefor
Grant 7,247,552 - Pozder , et al. July 24, 2
2007-07-24
Integrated circuit having structural support for a flip-chip interconnect pad and method therefor
App 20060154470 - Pozder; Scott K. ;   et al.
2006-07-13

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