Wijeratne; Sapumal

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wijeratne; Sapumal.The latest application filed is for "fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method".

Company Profile

0.11.12

Wijeratne; Sapumal - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method Grant 11,275,663 - Gendler , et al. March 15, 2	2022-03-15
Fast Dynamic Capacitance, Frequency, And/or Voltage Throttling Apparatus And Method App 20210382805 - Gendler; Alexander ; et al.	2021-12-09
Ultra low voltage, low leakage, high density, variation tolerant memory bit cells Grant 7,656,702 - Wijeratne , et al. February 2, 2	2010-02-02
Ultra low voltage, low leakage, high density, variation tolerant memory bit cells App 20090168509 - Wijeratne; Sapumal ; et al.	2009-07-02
Carry-skip adder having merged carry-skip cells with sum cells Grant 7,516,173 - Wijeratne April 7, 2	2009-04-07
Methods and apparatuses for operating memory App 20090086556 - Wijeratne; Sapumal ; et al.	2009-04-02
Sparse tree adder circuit Grant 7,509,368 - Anders , et al. March 24, 2	2009-03-24
Adder circuit with sense-amplifier multiplexer front-end Grant 7,325,024 - Mathew , et al. January 29, 2	2008-01-29
Single stage level restore circuit with hold functionality Grant 7,202,703 - Wijeratne April 10, 2	2007-04-10
Ratioed logic circuits with contention interrupt Grant 7,161,389 - Wijeratne , et al. January 9, 2	2007-01-09
Sparse tree adder circuit App 20060253523 - Anders; Mark A. ; et al.	2006-11-09
Leakage tolerant register file Grant 7,002,855 - Wijeratne , et al. February 21, 2	2006-02-21
Carry-skip adder having merged carry-skip cells with sum cells App 20060031280 - Wijeratne; Sapumal	2006-02-09
Ratioed logic circuits with contention interrupt App 20060001452 - Wijeratne; Sapumal ; et al.	2006-01-05
Single stage, level restore circuit with mixed signal inputs Grant 6,958,629 - Wijeratne October 25, 2	2005-10-25
Single stage level restore circuit with hold functionality App 20050169074 - Wijeratne, Sapumal	2005-08-04
Single Stage, Level Restore Circuit With Mixed Signal Inputs App 20050168244 - Wijeratne, Sapumal	2005-08-04
Select logic for low voltage swing circuits Grant 6,922,082 - Wijeratne July 26, 2	2005-07-26
Adder circuit with sense-amplifier multiplexer front-end App 20050125481 - Mathew, Sanu K. ; et al.	2005-06-09
Leakage tolerant register file App 20050068827 - Wijeratne, Sapumal ; et al.	2005-03-31
Select Logic For Low Voltage Swing Circuits App 20050068065 - Wijeratne, Sapumal	2005-03-31
Method and apparatus for fully automated signal integrity analysis for domino circuitry Grant 6,836,755 - Nardin , et al. December 28, 2	2004-12-28
Method And Apparatus For Fully Automated Signal Integrity Analysis For Domino Circuitry App 20030078764 - NARDIN, MARK D. ; et al.	2003-04-24

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