loadpatents
name:-0.0052230358123779
name:-0.021498918533325
name:-0.00053977966308594
Widmann; Dietrich Patent Filings

Widmann; Dietrich

Patent Applications and Registrations

Patent applications and USPTO patent grants for Widmann; Dietrich.The latest application filed is for "field-effect-controlled transistor and method for fabricating the transistor".

Company Profile
0.18.3
  • Widmann; Dietrich - late of Unterhaching DE
  • Widmann; Dietrich - Glen Allen VA
  • Widmann; Dietrich - Unterhaching DE
  • Widmann; Dietrich - Munchen DT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Lithography method and lithography mask
Grant 6,686,098 - Czech , et al. February 3, 2
2004-02-03
Contact hole fabrication with the aid of mutually crossing sudden phase shift edges of a single phase shift mask
Grant 6,635,388 - Friedrich , et al. October 21, 2
2003-10-21
Double gated transistor
Grant 6,503,784 - Enders , et al. January 7, 2
2003-01-07
Method for producing a semiconductor memory device with a multiplicity of memory cells
Grant 6,468,812 - Widmann , et al. October 22, 2
2002-10-22
Double gated transistor
Grant 6,459,123 - Enders , et al. October 1, 2
2002-10-01
Field-effect-controlled transistor and method for fabricating the transistor
App 20020014669 - Widmann, Dietrich ;   et al.
2002-02-07
Lithography method and lithography mask
App 20010021475 - Czech, G?uuml;nther ;   et al.
2001-09-13
Method for producing a semiconductor memory device
App 20010012658 - Widmann, Dietrich ;   et al.
2001-08-09
Memory cell having trench capacitor and vertical, dual-gated transistor
Grant 6,262,448 - Enders , et al. July 17, 2
2001-07-17
Ferroelectric memory device and method for producing the device
Grant 5,869,860 - Widmann , et al. February 9, 1
1999-02-09
Method of manufacturing stable, low resistance contacts in integrated semiconductor circuits
Grant 4,562,640 - Widmann , et al. January 7, 1
1986-01-07
Method of making MIS-field effect transistor having a short channel length
Grant 4,382,826 - Pfleiderer , et al. May 10, 1
1983-05-10
Method of producing low-resistance diffused regions in IC MOS semiconductor circuits in silicon-gate technology metal silicide layer formation
Grant 4,356,622 - Widmann November 2, 1
1982-11-02
Method of producing integrated MOS circuits via silicon gate technology
Grant 4,313,256 - Widmann February 2, 1
1982-02-02
MIS-field effect transistor having a short channel length and method of making the same
Grant 4,291,321 - Pfleiderer , et al. September 22, 1
1981-09-22
Arrangement with several thermal elements in series connection
Grant 4,211,888 - Stein , et al. July 8, 1
1980-07-08
Process for the production of fine structures consisting of a vapor-deposited material on a base
Grant 4,108,717 - Widmann August 22, 1
1978-08-22
Process for the automatic adjustment of semiconductor wafers
Grant 4,090,068 - Widmann , et al. May 16, 1
1978-05-16
Process for the production of a bipolar integrated circuit
Grant 4,047,975 - Widmann September 13, 1
1977-09-13
Semiconductors covered by a polymeric heat resistant relief structure
Grant 3,953,877 - Sigusch , et al. April 27, 1
1976-04-27
Contact Exposure Mask For The Selective Exposure Of Photovarnish Coatings For Semiconductor Purposes
Grant 3,644,134 - Widmann , et al. February 22, 1
1972-02-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed