Whittaker; Bruce E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Whittaker; Bruce E..The latest application filed is for "apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit".

Company Profile

0.16.0

Whittaker; Bruce E. - Mission Viejo CA
Whittaker; Bruce E. - San Juan Capistrano CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit Grant 6,070,166 - Whittaker , et al. May 30, 2	2000-05-30
Cache memory system and method for accessing a coincident cache with a bit-sliced architecture Grant 5,689,680 - Whittaker , et al. November 18, 1	1997-11-18
Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles Grant 5,598,551 - Barajas , et al. January 28, 1	1997-01-28
Programmable, multi-purpose virtual pin multiplier Grant 5,561,773 - Kalish , et al. October 1, 1	1996-10-01
Mini cache operational module for enhancement to general cache Grant 5,537,609 - Whittaker , et al. July 16, 1	1996-07-16
Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures Grant 5,506,967 - Barajas , et al. April 9, 1	1996-04-09
Inter-processor communication net Grant 5,459,836 - Whittaker , et al. October 17, 1	1995-10-17
System for halting synchronous digital modules Grant 5,355,468 - Jeppesen, III , et al. October 11, 1	1994-10-11
Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests Grant 5,146,596 - Whittaker , et al. September 8, 1	1992-09-08
System for memory data integrity Grant 5,117,428 - Jeppesen, III , et al. May 26, 1	1992-05-26
Width-expansible memory integrity structure Grant 5,088,092 - Jeppesen, III , et al. February 11, 1	1992-02-11
Method of providing flexibility and alterability in VLSI gate array chips Grant 5,087,839 - Whittaker , et al. February 11, 1	1992-02-11
Clocked logic circuitry preventing double driving on shared data bus Grant 5,086,427 - Whittaker , et al. February 4, 1	1992-02-04
Power control network for multiple digital modules Grant 4,677,566 - Whittaker , et al. June 30, 1	1987-06-30
System control network for multiple processor modules Grant 4,658,353 - Whittaker , et al. April 14, 1	1987-04-14
Power control network using reliable communications protocol Grant 4,635,195 - Jeppesen, III , et al. January 6, 1	1987-01-06

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