White; Ted R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for White; Ted R..The latest application filed is for "split-gate non-volatile memory cells having improved overlap tolerance".

Company Profile

0.46.41

White; Ted R. - Austin TX
White; Ted R. - Crolles FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Split-gate non-volatile memory cells having improved overlap tolerance Grant 9,111,908 - White , et al. August 18, 2	2015-08-18
Method of forming a shared contact in a semiconductor device Grant 8,426,310 - Adetutu , et al. April 23, 2	2013-04-23
Electronic device including a heterojunction region Grant 8,390,026 - Winstead , et al. March 5, 2	2013-03-05
Split-gate Non-volatile Memory Cells Having Improved Overlap Tolerance App 20120241839 - WHITE; TED R. ; et al.	2012-09-27
Split-gate non-volatile memory cell having improved overlap tolerance and method therefor Grant 8,163,615 - White , et al. April 24, 2	2012-04-24
Modified hybrid orientation technology Grant 8,125,032 - Adetutu , et al. February 28, 2	2012-02-28
Method Of Forming A Shared Contact In A Semiconductor Device App 20110294292 - Adetutu; Olubunmi O. ; et al.	2011-12-01
Method for making a semiconductor structure using silicon germanium Grant 7,927,956 - Orlowski , et al. April 19, 2	2011-04-19
Split gate non-volatile memory cell with improved endurance and method therefor Grant 7,923,769 - White , et al. April 12, 2	2011-04-12
Split gate non-volatile memory cell with improved endurance and method therefor Grant 7,923,328 - White , et al. April 12, 2	2011-04-12
Split Gate Non-volatile Memory Cell With Improved Endurance And Method Therefor App 20110031548 - WHITE; TED R. ; et al.	2011-02-10
Electronic devices including a semiconductor layer Grant 7,821,067 - Thean , et al. October 26, 2	2010-10-26
Method for forming a semiconductor structure having a strained silicon layer Grant 7,811,382 - Sadaka , et al. October 12, 2	2010-10-12
Twisted dual-substrate orientation (DSO) substrates Grant 7,803,670 - White , et al. September 28, 2	2010-09-28
Transistor with asymmetry for data storage circuitry Grant 7,799,644 - White , et al. September 21, 2	2010-09-21
Semiconductor device structure Grant 7,781,840 - White , et al. August 24, 2	2010-08-24
Step height reduction between SOI and EPI for DSO and BOS integration Grant 7,749,829 - Karve , et al. July 6, 2	2010-07-06
Integrated circuit with different channel materials for P and N channel transistors and method therefor Grant 7,700,420 - Thean , et al. April 20, 2	2010-04-20
Split Gate Non-volatile Memory Cell With Improved Endurance And Method Therefor App 20090256191 - White; Ted R. ; et al.	2009-10-15
Modified Hybrid Orientation Technology App 20090218625 - Adetutu; Olubunmi O. ; et al.	2009-09-03
Method for forming vertical structures in a semiconductor device Grant 7,556,992 - Shi , et al. July 7, 2	2009-07-07
Trench liner for DSO integration Grant 7,544,548 - Sadaka , et al. June 9, 2	2009-06-09
Modified hybrid orientation technology Grant 7,524,707 - Adetutu , et al. April 28, 2	2009-04-28
Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor Grant 7,494,856 - Zhang , et al. February 24, 2	2009-02-24
Semiconductor device with stressors and method therefor Grant 7,479,422 - Winstead , et al. January 20, 2	2009-01-20
Step height reduction between SOI and EPI for DSO and BOS integration App 20080274594 - Karve; Gauri V. ; et al.	2008-11-06
Method of making a multiple crystal orientation semiconductor device Grant 7,402,477 - Sadaka , et al. July 22, 2	2008-07-22
Electronic Device Including A Heterojunction Region And A Process For Forming The Electronic Device App 20080111153 - Winstead; Brian A. ; et al.	2008-05-15
Method for forming vertical structures in a semiconductor device App 20080023803 - Shi; Zhonghai ; et al.	2008-01-31
Transistor With Asymmetry For Data Storage Circuitry App 20080026529 - White; Ted R. ; et al.	2008-01-31
Twisted Dual-Substrate Orientation (DSO) Substrates App 20080020515 - White; Ted R. ; et al.	2008-01-24
Trench liner for DSO integration App 20070281436 - Sadaka; Mariam G. ; et al.	2007-12-06
Method For Forming A Semiconductor Structure Having A Strained Silicon Layer App 20070277728 - Sadaka; Mariam G. ; et al.	2007-12-06
Electronic Devices Including A Semiconductor Layer App 20070272952 - Thean; Voon-Yew ; et al.	2007-11-29
Hybrid Transistor Structure and a Method for Making the Same App 20070257322 - Shi; Zhonghai ; et al.	2007-11-08
SOI active layer with different surface orientation Grant 7,288,458 - Adetutu , et al. October 30, 2	2007-10-30
Method to selectively form regions having differing properties and structure Grant 7,285,452 - Sadaka , et al. October 23, 2	2007-10-23
Integrated circuit with different channel materials for P and N channel transistors and method therefor App 20070241403 - Thean; Voon-Yew ; et al.	2007-10-18
Method of making a dual strained channel semiconductor device Grant 7,282,402 - Sadaka , et al. October 16, 2	2007-10-16
Semiconductor Device Structure And Method Therefor App 20070235807 - White; Ted R. ; et al.	2007-10-11
Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor App 20070238250 - Zhang; Da ; et al.	2007-10-11
Method of making a multiple crystal orientation semiconductor device App 20070238233 - Sadaka; Mariam G. ; et al.	2007-10-11
Semiconductor device with stressors and method therefor App 20070210314 - Winstead; Brian A. ; et al.	2007-09-13
Electronic devices including a semiconductor layer and a process for forming the same Grant 7,265,004 - Thean , et al. September 4, 2	2007-09-04
Method to selectively form regions having differing properties and structure App 20070190745 - Sadaka; Mariam G. ; et al.	2007-08-16
Graded semiconductor layer Grant 7,241,647 - Sadaka , et al. July 10, 2	2007-07-10
SOI active layer with different surface orientation App 20070134891 - Adetutu; Olubunmi O. ; et al.	2007-06-14
Transistor fabrication using double etch/refill process Grant 7,226,820 - Zhang , et al. June 5, 2	2007-06-05
Semiconductor device structure and method therefor Grant 7,226,833 - White , et al. June 5, 2	2007-06-05
Electronic devices including a semiconductor layer and a process for forming the same App 20070108481 - Thean; Voon-Yew ; et al.	2007-05-17
Template layer formation Grant 7,208,357 - Sadaka , et al. April 24, 2	2007-04-24
Semiconductor structure having strained semiconductor and method therefor Grant 7,205,210 - Barr , et al. April 17, 2	2007-04-17
Method For Making A Semiconductor Structure Using Silicon Germanium App 20070082453 - Orlowski; Marius K. ; et al.	2007-04-12
Modified hybrid orientation technology App 20070048919 - Adetutu; Olubunmi O. ; et al.	2007-03-01
Method for making a semiconductor structure using silicon germanium Grant 7,163,903 - Orlowski , et al. January 16, 2	2007-01-16
Channel orientation to enhance transistor performance Grant 7,160,769 - White , et al. January 9, 2	2007-01-09
Method of making a dual strained channel semiconductor device App 20060228851 - Sadaka; Mariam G. ; et al.	2006-10-12
Semiconductor device featuring an arched structure strained semiconductor layer App 20060226492 - Nguyen; Bich-Yen ; et al.	2006-10-12
Transistor fabrication using double etch/refill process App 20060228842 - Zhang; Da ; et al.	2006-10-12
Method of making a semiconductor device having an arched structure strained semiconductor layer App 20060228872 - Nguyen; Bich-Yen ; et al.	2006-10-12
Dual metal gate electrode semiconductor fabrication process and structure thereof Grant 7,074,664 - White , et al. July 11, 2	2006-07-11
Double gate device having a heterojunction source/drain and strained channel Grant 7,067,868 - Thean , et al. June 27, 2	2006-06-27
Semiconductor layer formation Grant 7,056,778 - Liu , et al. June 6, 2	2006-06-06
Semiconductor device structure and method therefor App 20060094169 - White; Ted R. ; et al.	2006-05-04
Low RC product transistors in SOI semiconductor process Grant 7,037,795 - Barr , et al. May 2, 2	2006-05-02
Low Rc Product Transistors In Soi Semiconductor Process App 20060084235 - Barr; Alexander L. ; et al.	2006-04-20
Channel orientation to enhance transistor performance App 20060084207 - White; Ted R. ; et al.	2006-04-20
Method of manufacturing SOI template layer Grant 7,029,980 - Liu , et al. April 18, 2	2006-04-18
Method For Forming A Semiconductor Device Having A Strained Channel And A Heterojunction Source/drain App 20060068553 - Thean; Voon-Yew ; et al.	2006-03-30
Double gate device having a heterojunction source/drain and strained channel App 20060065927 - Thean; Voon-Yew ; et al.	2006-03-30
Method for forming a semiconductor device having a strained channel and a heterojunction source/drain Grant 7,018,901 - Thean , et al. March 28, 2	2006-03-28
Graded semiconductor layer App 20060040433 - Sadaka; Mariam G. ; et al.	2006-02-23
Strained semiconductor devices and method for forming at least a portion thereof App 20060030093 - Zhang; Da ; et al.	2006-02-09
Method for making a semiconductor structure using silicon germanium App 20050245092 - Orlowski, Marius K. ; et al.	2005-11-03
Semiconductor structure having strained semiconductor and method therefor App 20050181549 - Barr, Alexander L. ; et al.	2005-08-18
Template layer formation App 20050070053 - Sadaka, Mariam G. ; et al.	2005-03-31
SOI template layer App 20050070056 - Liu, Chun-Li ; et al.	2005-03-31
Semiconductor layer formation App 20050070057 - Liu, Chun-Li ; et al.	2005-03-31
Method for forming a double-gated semiconductor device Grant 6,838,322 - Pham , et al. January 4, 2	2005-01-04
Semiconductor structure with different lattice constant materials and method for forming the same Grant 6,831,350 - Liu , et al. December 14, 2	2004-12-14
Method For Forming A Double-gated Semiconductor Device App 20040219722 - Pham, Daniel T. ; et al.	2004-11-04
Process for forming a semiconductor device with an antireflective layer Grant 5,918,147 - Filipiak , et al. June 29, 1	1999-06-29
Process for fabricating a non-silicided region in an integrated circuit Grant 5,589,423 - White , et al. December 31, 1	1996-12-31
Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide Grant 4,902,533 - White , et al. February 20, 1	1990-02-20

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