Wetter; Holger

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wetter; Holger.The latest application filed is for "single ended bitline current sense amplifiers".

Company Profile

0.13.13

Wetter; Holger - Baden-Wuerttemberg DE
Wetter; Holger - Weil im Schoenbuch DE
Wetter; Holger - Weil im Schoebuch DE
Wetter, Holger - Well im Schoembuch DE
Wetter; Holger - Boblingen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Single Ended Bitline Current Sense Amplifiers App 20220230678 - Chakraborty; Sudipto ; et al.	2022-07-21
Layouting of interconnect lines in integrated circuits Grant 10,579,773 - Keinert , et al.	2020-03-03
Layouting of interconnect lines in integrated circuits Grant 10,417,377 - Keinert , et al. Sept	2019-09-17
Layouting Of Interconnect Lines In Integrated Circuits App 20180285513 - Keinert; Joachim ; et al.	2018-10-04
Layouting Of Interconnect Lines In Integrated Circuits App 20180285514 - Keinert; Joachim ; et al.	2018-10-04
Layouting of interconnect lines in integrated circuits Grant 10,013,521 - Keinert , et al. July 3, 2	2018-07-03
Enabling an incremental sign-off process using design data Grant 9,922,154 - Anderson , et al. March 20, 2	2018-03-20
NAND-based write driver for SRAM Grant 9,837,143 - Anderson , et al. December 5, 2	2017-12-05
Enabling An Incremental Sign-off Process Using Design Data App 20170337314 - Anderson; Hans-Werner ; et al.	2017-11-23
Write-bitline control in multicore SRAM arrays Grant 9,761,304 - Keinert , et al. September 12, 2	2017-09-12
Layouting Of Interconnect Lines In Integrated Circuits App 20170140088 - Keinert; Joachim ; et al.	2017-05-18
Incorporating synthesized netlists as subcomponents in a hierarchical custom design Grant 8,560,983 - Brandt , et al. October 15, 2	2013-10-15
Incorporating Synthesized Netlists as Subcomponents in a Hierarchical Custom Design App 20130145329 - Brandt; Uwe ; et al.	2013-06-06
Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result Grant 8,332,453 - Boersma , et al. December 11, 2	2012-12-11
Fast routing of custom macros Grant 8,286,115 - Wetter , et al. October 9, 2	2012-10-09
System and method for scanning sequential logic elements Grant 7,913,132 - Gemmeke , et al. March 22, 2	2011-03-22
Method for calculating a result of a division with a floating point unit with fused multiply-add Grant 7,873,687 - Gerwig , et al. January 18, 2	2011-01-18
Shifter With All-one And All-zero Detection App 20100146023 - Boersma; Maarten ; et al.	2010-06-10
Fast Routing Of Custom Macros App 20100146471 - Wetter; Holger ; et al.	2010-06-10
System and Method for Scanning Sequential Logic Elements App 20090135961 - Gemmeke; Tobias ; et al.	2009-05-28
Method for Calculating a Result of a Division with a Floating Point Unit with Fused Multiply-Add App 20070083583 - Gerwig; Guenter ; et al.	2007-04-12
Highly parallel structure for fast multi cycle binary and decimal adder unit App 20060031279 - Haller; Wilhelm ; et al.	2006-02-09
Fast integer division with minimum number of iterations in substraction-based hardware divide processor App 20040249877 - Gerwig, Guenter ; et al.	2004-12-09
Binary and decimal adder unit Grant 6,292,819 - Bultmann , et al. September 18, 2	2001-09-18

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