loadpatents
name:-0.019622802734375
name:-0.019222974777222
name:-0.0014610290527344
West; David Ian Patent Filings

West; David Ian

Patent Applications and Registrations

Patent applications and USPTO patent grants for West; David Ian.The latest application filed is for "dynamic random access memory (dram) backchannel communication systems and methods".

Company Profile
1.18.19
  • West; David Ian - San Diego CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Dynamic random access memory (DRAM) backchannel communication systems and methods
Grant 10,224,081 - West , et al.
2019-03-05
Protecting an ECC location when transmitting correction data across a memory link
Grant 10,140,175 - West , et al. Nov
2018-11-27
Memory array and link error correction in a low power memory sub-system
Grant 10,061,645 - Suh , et al. August 28, 2
2018-08-28
Separate link and array error correction in a memory system
Grant 9,965,352 - Suh , et al. May 8, 2
2018-05-08
Dynamic Random Access Memory (dram) Backchannel Communication Systems And Methods
App 20180114553 - West; David Ian ;   et al.
2018-04-26
Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses
Grant 9,947,377 - Srinivas , et al. April 17, 2
2018-04-17
Dynamic random access memory (DRAM) backchannel communication systems and methods
Grant 9,881,656 - West , et al. January 30, 2
2018-01-30
Method and apparatus for routing die signals using external interconnects
Grant 9,871,012 - Srinivas , et al. January 16, 2
2018-01-16
Providing Memory Training Of Dynamic Random Access Memory (dram) Systems Using Port-to-port Loopbacks, And Related Methods, Systems, And Apparatuses
App 20170278554 - Srinivas; Vaishnav ;   et al.
2017-09-28
Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses
Grant 9,767,868 - Srinivas , et al. September 19, 2
2017-09-19
Separate Link And Array Error Correction In A Memory System
App 20170147432 - SUH; Jungwon ;   et al.
2017-05-25
Protecting An Ecc Location When Transmitting Correction Data Across A Memory Link
App 20170147431 - WEST; David Ian ;   et al.
2017-05-25
Dynamic control of signaling power based on an error rate
Grant 9,633,698 - Chun , et al. April 25, 2
2017-04-25
Memory Array And Link Error Correction In A Low Power Memory Sub-system
App 20170004035 - SUH; Jungwon ;   et al.
2017-01-05
Data Bandwidth Scalable Memory System
App 20160291634 - SUH; Jungwon ;   et al.
2016-10-06
Clock and data recovery with high jitter tolerance and fast phase locking
Grant 9,281,934 - Song , et al. March 8, 2
2016-03-08
Dynamic Control Of Signaling Power Based On An Error Rate
App 20150332735 - CHUN; Dexter Tamio ;   et al.
2015-11-19
Clock And Data Recovery With High Jitter Tolerance And Fast Phase Locking
App 20150318978 - Song; Yu ;   et al.
2015-11-05
Package on package (PoP) integrated device comprising a redistribution layer
Grant 9,153,560 - Lane , et al. October 6, 2
2015-10-06
Serial Data Transmission For Dynamic Random Access Memory (dram) Interfaces
App 20150213850 - Srinivas; Vaishnav ;   et al.
2015-07-30
Providing Memory Training Of Dynamic Random Access Memory (dram) Systems Using Port-to-port Loopbacks, And Related Methods, Systems, And Apparatuses
App 20150213849 - Srinivas; Vaishnav ;   et al.
2015-07-30
PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A REDISTRIBUTION LAYER
App 20150206854 - Lane; Ryan David ;   et al.
2015-07-23
Dynamic Random Access Memory (dram) Backchannel Communication Systems And Methods
App 20150194197 - West; David Ian ;   et al.
2015-07-09
Integrated circuit floorplan for compact clock distribution
Grant 9,032,358 - Srinivas , et al. May 12, 2
2015-05-12
Measure-based delay circuit
Grant 8,957,714 - Srinivas , et al. February 17, 2
2015-02-17
Measure-Based Delay Circuit
App 20140266357 - Srinivas; Vaishnav ;   et al.
2014-09-18
Integrated Circuit Floorplan For Compact Clock Distribution
App 20140253228 - Srinivas; Vaishnav ;   et al.
2014-09-11
Method And Apparatus For Routing Die Signals Using External Interconnects
App 20140061642 - Srinivas; Vaishnav ;   et al.
2014-03-06
Semiconductor device metal programmable pooling and dies
Grant 8,392,865 - Malekkhosravi , et al. March 5, 2
2013-03-05
Die apparatus having configurable input/output and control method thereof
Grant 8,072,240 - Malekkhosravi , et al. December 6, 2
2011-12-06
Semiconductor Device Metal Programmable Pooling And Dies
App 20110121467 - Malekkhosravi; Behnam ;   et al.
2011-05-26
Semiconductor device metal programmable pooling and dies
Grant 7,882,453 - Malekkhosravi , et al. February 1, 2
2011-02-01
Die Apparatus Having Configurable Input/output And Control Method Thereof
App 20100073026 - Malekkhosravi; Behnam ;   et al.
2010-03-25
Die apparatus having configurable input/output and control method thereof
Grant 7,642,809 - Malekkhosravi , et al. January 5, 2
2010-01-05
Semiconductor Device Metal Programmable Pooling And Dies
App 20090106723 - MALEKKHOSRAVI; Behnam ;   et al.
2009-04-23
Die Apparatus Having Configurable Input/output And Control Method Thereof
App 20080186053 - Malekkhosravi; Behnam ;   et al.
2008-08-07

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