loadpatents
name:-0.016847848892212
name:-0.010010957717896
name:-0.008350133895874
Weng; Li-Sheng Patent Filings

Weng; Li-Sheng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Weng; Li-Sheng.The latest application filed is for "fan-out wafer-level packaging (fowlp) integrated circuits (ics) employing an electro-magnetic interference (emi) shield structure in unused fan-out area for emi shielding, and related fabrication methods".

Company Profile
7.8.12
  • Weng; Li-Sheng - San Diego CA
  • Weng; Li-Sheng - Chandler AZ
  • Weng; Li-Sheng - Tempe AZ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Repurposed seed layer for high frequency noise control and electrostatic discharge connection
Grant 11,380,613 - Li , et al. July 5, 2
2022-07-05
FAN-OUT WAFER-LEVEL PACKAGING (FOWLP) INTEGRATED CIRCUITS (ICs) EMPLOYING AN ELECTRO-MAGNETIC INTERFERENCE (EMI) SHIELD STRUCTURE IN UNUSED FAN-OUT AREA FOR EMI SHIELDING, AND RELATED FABRICATION METHODS
App 20220199547 - Weng; Li-Sheng ;   et al.
2022-06-23
Package Comprising A Substrate And A High-density Interconnect Integrated Device
App 20220149005 - SUN; Yangyang ;   et al.
2022-05-12
Repurposed Seed Layer For High Frequency Noise Control And Electrostatic Discharge Connection
App 20210375742 - LI; Yue ;   et al.
2021-12-02
Microelectronic package having electromagnetic interference shielding
Grant 11,189,574 - Weng , et al. November 30, 2
2021-11-30
Package comprising a substrate having a via wall configured as a shield
Grant 11,139,224 - Zhang , et al. October 5, 2
2021-10-05
Package Comprising A Substrate And A High-density Interconnect Integrated Device Coupled To The Substrate
App 20210296246 - LANE; Ryan ;   et al.
2021-09-23
Package Comprising A Substrate Having A Via Wall Configured As A Shield
App 20210175152 - ZHANG; Chaoqi ;   et al.
2021-06-10
Integrated Device Comprising Interconnect Structures Having An Inner Interconnect, A Dielectric Layer And A Conductive Layer
App 20210125951 - WENG; Li-Sheng ;   et al.
2021-04-29
Microelectronic Package Having Electromagnetic Interference Shielding
App 20210118809 - Weng; Li-Sheng ;   et al.
2021-04-22
Conductive coating for a microelectronics package
Grant 10,910,314 - Weng , et al. February 2, 2
2021-02-02
Solder resist layer structures for terminating de-featured components and methods of making the same
Grant 10,658,198 - Weng , et al.
2020-05-19
Conductive Coating For A Microelectronics Package
App 20200118930 - Weng; Li-Sheng ;   et al.
2020-04-16
Conductive coating for a microelectronics package
Grant 10,510,667 - Weng , et al. Dec
2019-12-17
Solder Resist Layer Structures For Terminating De-featured Components And Methods Of Making The Same
App 20190181017 - Weng; Li-Sheng ;   et al.
2019-06-13
Solder resist layer structures for terminating de-featured components and methods of making the same
Grant 10,244,632 - Weng , et al.
2019-03-26
Solder Resist Layer Structures For Terminating De-featured Components And Methods Of Making The Same
App 20180255640 - Weng; Li-Sheng ;   et al.
2018-09-06
Conductive Coating For A Microelectronics Package
App 20180174972 - Weng; Li-Sheng ;   et al.
2018-06-21
Integrated circuit package including floating package stiffener
Grant 9,900,976 - Chen , et al. February 20, 2
2018-02-20
On Package Floating Metal/Stiffener Grounding to Mitigate RFI and SI Risks
App 20160268213 - JIANG; Hongjin ;   et al.
2016-09-15

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