loadpatents
Patent applications and USPTO patent grants for Wen; Ming-Chang.The latest application filed is for "dielectric spacer to prevent contacting shorting".
Patent | Date |
---|---|
Dielectric Spacer to Prevent Contacting Shorting App 20220285529 - Chen; Ting-Gang ;   et al. | 2022-09-08 |
Method for forming semiconductor device Grant 11,437,278 - Chang , et al. September 6, 2 | 2022-09-06 |
Sram Structure And Method For Forming The Same App 20220254789 - WEN; MING-CHANG ;   et al. | 2022-08-11 |
Semiconductor device having nanosheet transistor and methods of fabrication thereof Grant 11,387,322 - Wang , et al. July 12, 2 | 2022-07-12 |
Dielectric spacer to prevent contacting shorting Grant 11,342,444 - Chen , et al. May 24, 2 | 2022-05-24 |
Cut Metal Gate Process For Reducing Transistor Spacing App 20220157595 - Wen; Ming-Chang ;   et al. | 2022-05-19 |
SRAM structure and method for forming the same Grant 11,315,933 - Wen , et al. April 26, 2 | 2022-04-26 |
Semiconductor Device Having Nanosheet Transistor And Methods Of Fabrication Thereof App 20220093743 - WANG; Chih-Ching ;   et al. | 2022-03-24 |
Profile Control Of A Gap Fill Structure App 20220077001 - WU; Wan-Yao ;   et al. | 2022-03-10 |
Cut metal gate process for reducing transistor spacing Grant 11,239,072 - Wen , et al. February 1, 2 | 2022-02-01 |
Profile control of a gap fill structure Grant 11,177,180 - Wu , et al. November 16, 2 | 2021-11-16 |
Structure and method for alignment marks Grant 11,121,128 - Wen , et al. September 14, 2 | 2021-09-14 |
Dielectric spacer to prevent contacting shorting Grant 11,107,902 - Chen , et al. August 31, 2 | 2021-08-31 |
Profile Control Of A Gap Fill Structure App 20210249309 - Wu; Wan-Yao ;   et al. | 2021-08-12 |
Etch Stop Layer Between Substrate and Isolation Structure App 20210242090 - Wen; Ming-Chang ;   et al. | 2021-08-05 |
Local Gate Height Tuning by Cmp And Dummy Gate Design App 20210202320 - Wen; Ming-Chang ;   et al. | 2021-07-01 |
Structure For Fringing Capacitance Control App 20210193530 - CHEN; Keng-Yao ;   et al. | 2021-06-24 |
Etch stop layer between substrate and isolation structure Grant 10,991,628 - Wen , et al. April 27, 2 | 2021-04-27 |
Etch stop layer between substrate and isolation structure Grant 10,978,351 - Wen , et al. April 13, 2 | 2021-04-13 |
Creating devices with multiple threshold voltages by cut-metal-gate process Grant 10,868,003 - Wen , et al. December 15, 2 | 2020-12-15 |
Method For Forming Semiconductor Device App 20200365465 - CHANG; Chang-Yun ;   et al. | 2020-11-19 |
Structure and Method for Alignment Marks App 20200286887 - Wen; Ming-Chang ;   et al. | 2020-09-10 |
Semiconductor device having a metal gate and formation method thereof Grant 10,741,450 - Chang , et al. A | 2020-08-11 |
Cut Metal Gate Process for Reducing Transistor Spacing App 20200251325 - Kind Code | 2020-08-06 |
Structure and method for alignment marks Grant 10,665,585 - Wen , et al. | 2020-05-26 |
Cut metal gate process for reducing transistor spacing Grant 10,651,030 - Wen , et al. | 2020-05-12 |
Etch Stop Layer Between Substrate and Isolation Structure App 20200091008 - Wen; Ming-Chang ;   et al. | 2020-03-19 |
Creating Devices with Multiple Threshold Voltages by Cut-Metal-Gate Process App 20200058650 - Wen; Ming-Chang ;   et al. | 2020-02-20 |
Dielectric Spacer to Prevent Contacting Shorting App 20200013875 - Chen; Ting-Gang ;   et al. | 2020-01-09 |
Sram Structure And Method For Forming The Same App 20200006354 - WEN; MING-CHANG ;   et al. | 2020-01-02 |
Dielectric Spacer to Prevent Contacting Shorting App 20190393324 - Chen; Ting-Gang ;   et al. | 2019-12-26 |
Creating devices with multiple threshold voltage by cut-metal-gate process Grant 10,461,078 - Wen , et al. Oc | 2019-10-29 |
Cut Metal Gate Process for Reducing Transistor Spacing App 20190318922 - Wen; Ming-Chang ;   et al. | 2019-10-17 |
Creating Devices with Multiple Threshold Voltage by Cut-Metal-Gate Process App 20190267372 - Wen; Ming-Chang ;   et al. | 2019-08-29 |
Cut metal gate process for reducing transistor spacing Grant 10,319,581 - Wen , et al. | 2019-06-11 |
Semiconductor Device And Formation Method Thereof App 20190164838 - CHANG; Chang-Yun ;   et al. | 2019-05-30 |
Cut Metal Gate Process for Reducing Transistor Spacing App 20190164741 - Wen; Ming-Chang ;   et al. | 2019-05-30 |
Etch Stop Layer Between Substrate and Isolation Structure App 20190157159 - Wen; Ming-Chang ;   et al. | 2019-05-23 |
Structure and method for overlay marks Grant 10,163,738 - Wang , et al. Dec | 2018-12-25 |
Structure And Method For Overlay Marks App 20170084506 - WANG; Hsien-Cheng ;   et al. | 2017-03-23 |
Structure and method for overlay marks Grant 9,543,406 - Wang , et al. January 10, 2 | 2017-01-10 |
Medication Dispensing System And Method And Non-stationary Computer Readable Recording Medium App 20160354284 - Liou; Yu-Cing ;   et al. | 2016-12-08 |
Cross quadrupole double lithography method using two complementary apertures Grant 9,280,041 - Wang , et al. March 8, 2 | 2016-03-08 |
Structure and Method for Alignment Marks App 20150214225 - Wen; Ming-Chang ;   et al. | 2015-07-30 |
Structure and method for alignment marks Grant 9,000,525 - Wen , et al. April 7, 2 | 2015-04-07 |
Double Dipole Lithography Method For Semiconductor Device Fabrication App 20130188164 - Wang; Hsien-Cheng ;   et al. | 2013-07-25 |
Cross quadrupole double lithography method and apparatus for semiconductor device fabrication using two apertures Grant 8,416,393 - Wang , et al. April 9, 2 | 2013-04-09 |
Structure And Method For Overlay Marks App 20120146159 - WANG; Hsien-Cheng ;   et al. | 2012-06-14 |
Structure and Method for Alignment Marks App 20110284966 - Wen; Ming-Chang ;   et al. | 2011-11-24 |
Lithography Method And Apparatus For Semiconductor Device Fabrication App 20100255679 - Wang; Hsien-Cheng ;   et al. | 2010-10-07 |
Process for preparing nanofluids with rotating packed bed reactor Grant 7,649,024 - Li , et al. January 19, 2 | 2010-01-19 |
Process for preparing nanofluids with rotating packed bed reactor App 20060247322 - Li; Chia-Chen ;   et al. | 2006-11-02 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.