Wen; Huajun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wen; Huajun.The latest application filed is for "dynamic power meter with improved accuracy and single cycle resolution".

Company Profile

1.14.12

Wen; Huajun - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dynamic power meter with improved accuracy and single cycle resolution Grant 10,345,882 - Wen , et al. July 9, 2	2019-07-09
Dynamic Power Meter with Improved Accuracy and Single Cycle Resolution App 20160291068 - Wen; Huajun ; et al.	2016-10-06
Reducing power grid noise in a processor while minimizing performance loss Grant 9,146,772 - Eisen , et al. September 29, 2	2015-09-29
Reducing power grid noise in a processor while minimizing performance loss Grant 9,141,421 - Eisen , et al. September 22, 2	2015-09-22
Minimizing power consumption for fixed-frequency processing unit operation Grant 9,052,905 - Allen-Ware , et al. June 9, 2	2015-06-09
Minimizing power consumption for fixed-frequency processing unit operation Grant 8,943,341 - Allen-Ware , et al. January 27, 2	2015-01-27
Processor voltage regulation Grant 8,812,879 - Wen , et al. August 19, 2	2014-08-19
Reducing Power Grid Noise In A Processor While Minimizing Performance Loss App 20140157277 - Eisen; Lee E. ; et al.	2014-06-05
Reducing Power Grid Noise In A Processor While Minimizing Performance Loss App 20140157033 - Eisen; Lee E. ; et al.	2014-06-05
Minimizing Power Consumption for Fixed-Frequency Processing Unit Operation App 20130268786 - Allen-Ware; Malcolm S. ; et al.	2013-10-10
Minimizing Power Consumption for Fixed-Frequency Processing Unit Operation App 20130268785 - Allen-Ware; Malcolm S. ; et al.	2013-10-10
Processor Voltage Regulation App 20110161682 - Wen; Huajun ; et al.	2011-06-30
Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic Grant 7,206,802 - Wen April 17, 2	2007-04-17
System and method for designing a circuit wherein a single timing analysis ensures adequate performance in multiple applications Grant 7,024,647 - Wen April 4, 2	2006-04-04
System and method for designing a circuit wherein a single timing analysis ensures adequate performance in multiple applications App 20050015737 - Wen, Huajun	2005-01-20
Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic App 20040073593 - Wen, Huajun	2004-04-15
Phase manipulation of intertwined bus signals for reduction of hostile coupling in integrated circuit interconnects Grant 6,718,420 - Badar , et al. April 6, 2	2004-04-06
Dynamic phase splitter circuit and method for low-noise and simultaneous production of true and complement dynamic logic signals Grant 6,664,836 - Wen December 16, 2	2003-12-16
Edge Triggered Latch With Symmetrical Paths From Clock To Data Outputs App 20020196064 - Kojima, Nobuo ; et al.	2002-12-26
Edge-triggered Latch With Balanced Pass-transistor Logic Trigger App 20020130693 - Kojima, Nobuo ; et al.	2002-09-19
Edge-triggered latch with symmetric complementary pass-transistor logic data path Grant 6,437,624 - Kojima , et al. August 20, 2	2002-08-20

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