Wei; Che-Chia
Patent Applications and Registrations
Patent applications and USPTO patent grants for Wei; Che-Chia.The latest application filed is for "method for fabricating interlevel contacts of aluminum/refractory metal alloys".
- Wei; Che-Chia - Plano TX
- Wei; Che-Chia - Singapore SG
- Wei; Che-Chia - Plano County TX
- Wei; Che-Chia - Wylie TX
| Patent | Date |
|---|---|
| Method for fabricating interlevel contacts of aluminum/refractory metal alloys Grant 6,617,242 - Chen , et al. September 9, 2 | 2003-09-09 |
| Having halo regions integrated circuit device structure Grant 5,894,158 - Wei April 13, 1 | 1999-04-13 |
| Semiconductor contact via structure Grant 5,841,195 - Lin , et al. November 24, 1 | 1998-11-24 |
| Method of forming an integrated circuit device Grant 5,837,587 - Wei November 17, 1 | 1998-11-17 |
| Semiconductor contact metallization Grant 5,677,238 - Gn , et al. October 14, 1 | 1997-10-14 |
| Method for making electrical local interconnects Grant 5,624,871 - Teo , et al. April 29, 1 | 1997-04-29 |
| Method of making back gate contact for silicon on insulator technology Grant 5,610,083 - Chan , et al. March 11, 1 | 1997-03-11 |
| Method for forming interconnect in integrated circuits Grant 5,595,935 - Chan , et al. January 21, 1 | 1997-01-21 |
| Self-aligned contact process Grant 5,369,303 - Wei November 29, 1 | 1994-11-29 |
| Method for fabricating an interconnect structure in an integrated circuit Grant 5,346,860 - Wei September 13, 1 | 1994-09-13 |
| Oxide-capped titanium silicide formation Grant 5,326,724 - Wei July 5, 1 | 1994-07-05 |
| Semiconductor contact via structure having amorphous silicon side walls Grant 5,317,192 - Chen , et al. May 31, 1 | 1994-05-31 |
| Method of forming a gate overlap LDD structure Grant 5,304,504 - Wei , et al. April 19, 1 | 1994-04-19 |
| Method of forming isolated regions of oxide Grant 5,260,229 - Hodges , et al. November 9, 1 | 1993-11-09 |
| Semiconductor contact via structure and method Grant 5,246,883 - Lin , et al. September 21, 1 | 1993-09-21 |
| Titanium silicide local interconnect process Grant 5,173,450 - Wei December 22, 1 | 1992-12-22 |
| Method for forming a metal contact Grant 5,108,951 - Chen , et al. April 28, 1 | 1992-04-28 |
| Oxide-isolated source/drain transistor Grant 5,043,778 - Teng , et al. August 27, 1 | 1991-08-27 |
| Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects Grant 5,010,032 - Tang , et al. April 23, 1 | 1991-04-23 |
| SRAM with local interconnect Grant 4,975,756 - Haken , et al. December 4, 1 | 1990-12-04 |
| Method of making oxide-isolated source/drain transistor Grant 4,963,502 - Teng , et al. October 16, 1 | 1990-10-16 |
| Selective silicidation process using a titanium nitride protective layer Grant 4,920,073 - Wei , et al. April 24, 1 | 1990-04-24 |
| CMOS device with both p+ and n+ gates Grant 4,890,141 - Tang , et al. December 26, 1 | 1989-12-26 |
| Process for formation of shallow silicided junctions Grant 4,788,160 - Havemann , et al. November 29, 1 | 1988-11-29 |
| Local interconnect Grant 4,746,219 - Holloway , et al. May 24, 1 | 1988-05-24 |
| Oxide-capped titanium silicide formation Grant 4,690,730 - Tang , et al. September 1, 1 | 1987-09-01 |
| Process to increase tin thickness Grant 4,676,866 - Tang , et al. June 30, 1 | 1987-06-30 |
| Process for patterning local interconnects Grant 4,657,628 - Holloway , et al. April 14, 1 | 1987-04-14 |
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