loadpatents
name:-0.022994995117188
name:-0.01813006401062
name:-0.0031499862670898
Wei; An Chyi Patent Filings

Wei; An Chyi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wei; An Chyi.The latest application filed is for "air spacers around contact plugs and method forming same".

Company Profile
5.19.26
  • Wei; An Chyi - Hsinchu TW
  • Wei; An Chyi - Hsinchu City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Air Spacers Around Contact Plugs and Method Forming Same
App 20220310820 - Huang; Chen-Huang ;   et al.
2022-09-29
Air Spacer and Method of Forming Same
App 20220285530 - Sie; Ming-Jhe ;   et al.
2022-09-08
FinFET device and method
Grant 11,437,498 - Wu , et al. September 6, 2
2022-09-06
Semiconductor Device and Method of Manufacture
App 20220262920 - Huang; Chen-Huang ;   et al.
2022-08-18
Nanostructure Field-Effect Transistor Device and Method of Forming
App 20220209023 - Chang; Cheng-Chung ;   et al.
2022-06-30
Air spacers around contact plugs and method forming same
Grant 11,355,616 - Huang , et al. June 7, 2
2022-06-07
Air spacer and method of forming same
Grant 11,349,014 - Sie , et al. May 31, 2
2022-05-31
Semiconductor device and method of manufacture
Grant 11,329,140 - Huang , et al. May 10, 2
2022-05-10
Nanostructure field-effect transistor device and method of forming
Grant 11,282,967 - Chang , et al. March 22, 2
2022-03-22
Air Spacer and Method of Forming Same
App 20210408266 - Sie; Ming-Jhe ;   et al.
2021-12-30
Fin Field-effect Transistor And Method Of Forming The Same
App 20210376114 - Hsiao; Hsu Ming ;   et al.
2021-12-02
Method For Forming Fin Field Effect Transistor (finfet) Device Structure
App 20210343711 - WU; Chung-Shu ;   et al.
2021-11-04
Semiconductor Device and Method of Manufacture
App 20210226033 - Huang; Chen-Huang ;   et al.
2021-07-22
Method for forming fin field effect transistor (FinFet) device structure
Grant 11,063,043 - Wu , et al. July 13, 2
2021-07-13
Nanostructure Field-effect Transistor Device And Method Of Forming
App 20210202756 - Chang; Cheng-Chung ;   et al.
2021-07-01
Air Spacers Around Contact Plugs and Method Forming Same
App 20210134973 - Huang; Chen-Huang ;   et al.
2021-05-06
Finfet Device And Method
App 20210111272 - Wu; Chung-Shu ;   et al.
2021-04-15
Method of forming semiconductor device and semiconductor device
Grant 10,879,074 - Jang , et al. December 29, 2
2020-12-29
FinFET device and method
Grant 10,861,960 - Wu , et al. December 8, 2
2020-12-08
Cut Metal Gate Processes
App 20200350172 - Jang; Shu-Uei ;   et al.
2020-11-05
Method Of Forming Semiconductor Device And Semiconductor Device
App 20200294804 - JANG; Shu-Uei ;   et al.
2020-09-17
Cut metal gate processes
Grant 10,714,347 - Jang , et al.
2020-07-14
Method of forming semiconductor structure and semiconductor device
Grant 10,672,613 - Jang , et al.
2020-06-02
Cut Metal Gate Processes
App 20200135472 - Jang; Shu-Uei ;   et al.
2020-04-30
Method For Forming Fin Field Effect Transistor (finfet) Device Structure
App 20200135725 - WU; Chung-Shu ;   et al.
2020-04-30
Fin field effect transistor (FinFET) device structure and method for forming the same
Grant 10,515,952 - Wu , et al. Dec
2019-12-24
Method Of Forming Semiconductor Structure And Semiconductor Device
App 20190157090 - JANG; Shu-Uei ;   et al.
2019-05-23
Method for forming fin field effect transistor (FinFET) device structure
Grant 10,276,449 - Wu , et al.
2019-04-30
Fin Field Effect Transistor (finfet) Device Structure And Method For Forming The Same
App 20190043857 - WU; Chung-Shu ;   et al.
2019-02-07
Composite hard mask etching profile for preventing pattern collapse in high-aspect-ratio trenches
Grant 9,449,821 - Yang , et al. September 20, 2
2016-09-20
High Aspect Ratio Structure
App 20160172294 - Chang; Sheng-Yuan ;   et al.
2016-06-16
Method of fabricating deep trench semiconductor devices, and deep trench semiconductor devices
Grant 9,349,746 - Yang , et al. May 24, 2
2016-05-24
Method of word-line formation by semi-damascene process with thin protective conductor layer
Grant 9,252,153 - Lung , et al. February 2, 2
2016-02-02
Method of Controlling Recess Depth and Bottom ECD in Over-Etching
App 20160020119 - Chang; Sheng-Yuan ;   et al.
2016-01-21
Composite Hard Mask Etching Profile for Preventing Pattern Collapse in High-Aspect-Ratio Trenches
App 20160020211 - Yang; Zusing ;   et al.
2016-01-21
Semiconductor Structure And Manufacturing Method Of The Same
App 20150194481 - Lai; Erh-Kun ;   et al.
2015-07-09
Method of forming self-aligned contacts and local interconnects
Grant 8,076,230 - Wei December 13, 2
2011-12-13
Process of forming a self-aligned contact in a semiconductor device
Grant 7,723,229 - Wei , et al. May 25, 2
2010-05-25
Method Of Forming Self-aligned Contacts And Local Interconnects
App 20090280633 - Wei; An Chyi
2009-11-12
Method of forming self-aligned contacts and local interconnects
Grant 7,575,990 - Wei August 18, 2
2009-08-18
Plasma etching methods using nitrogen memory species for sustaining glow discharge
Grant 7,410,593 - Lee , et al. August 12, 2
2008-08-12
Method of performing a pressure calibration during waferless autoclean process
App 20070246063 - Wei; An Chyi ;   et al.
2007-10-25
Plasma etching methods using nitrogen memory species for sustaining glow discharge
App 20070193977 - Lee; Hong-Ji ;   et al.
2007-08-23
Method of forming self-aligned contacts and local interconnects
App 20070004187 - Wei; An Chyi
2007-01-04
Process of forming a self-aligned contact in a semiconductor device
App 20060240654 - Wei; An Chyi ;   et al.
2006-10-26

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed