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name:-0.009270191192627
name:-0.0073909759521484
name:-0.0034909248352051
WEBER; Olivier Patent Filings

WEBER; Olivier

Patent Applications and Registrations

Patent applications and USPTO patent grants for WEBER; Olivier.The latest application filed is for "set of integrated standard cells".

Company Profile
3.12.17
  • WEBER; Olivier - Grenoble FR
  • Weber; Olivier - Lyon FR
  • Weber; Olivier - Roost Warendin FR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Set Of Integrated Standard Cells
App 20220199648 - WEBER; Olivier ;   et al.
2022-06-23
Integrated Circuit Including Bipolar Transistors
App 20220020816 - BOIVIN; Philippe ;   et al.
2022-01-20
Strained Transistors And Phase Change Memory
App 20210343788 - BERTHELON; Remy ;   et al.
2021-11-04
Integrated circuit including bipolar transistors
Grant 11,152,430 - Boivin , et al. October 19, 2
2021-10-19
Resistive RAM memory cell
Grant 10,482,957 - Boivin , et al. Nov
2019-11-19
Integrated Circuit Including Bipolar Transistors
App 20190312088 - BOIVIN; Philippe ;   et al.
2019-10-10
Method of forming MOS and bipolar transistors
Grant 10,381,344 - Weber , et al. A
2019-08-13
Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device
Grant 10,381,478 - Boeuf , et al. A
2019-08-13
Device comprising multiple gate structures and method of simultaneously manufacturing different transistors
Grant 10,332,808 - Julien , et al.
2019-06-25
Chip Containing An Onboard Non-volatile Memory Comprising A Phase-change Material
App 20190140176 - ARNAUD; Franck ;   et al.
2019-05-09
Resistive Ram Memory Cell
App 20180330780 - BOIVIN; Philippe ;   et al.
2018-11-15
Method Of Simultaneously Manufacturing Different Transistors
App 20180269115 - Julien; Franck ;   et al.
2018-09-20
Method Of Forming Mos And Bipolar Transistors
App 20180175022 - Weber; Olivier ;   et al.
2018-06-21
Fdsoi-type Field-effect Transistors
App 20180097014 - Barral; Vincent ;   et al.
2018-04-05
Method of forming MOS and bipolar transistors
Grant 9,929,146 - Weber , et al. March 27, 2
2018-03-27
Method of manufacturing a device with MOS transistors
Grant 9,876,032 - Chhun , et al. January 23, 2
2018-01-23
Method Of Forming Mos And Bipolar Transistors
App 20170271325 - Weber; Olivier ;   et al.
2017-09-21
Method Of Localized Modification Of The Stresses In A Substrate Of The Soi Type, In Particular Fd Soi Type, And Corresponding Device
App 20170213910 - Boeuf; Frederic ;   et al.
2017-07-27
Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device
Grant 9,653,538 - Boeuf , et al. May 16, 2
2017-05-16
Method Of Manufacturing A Device With Mos Transistors
App 20170117296 - Chhun; Sonarith ;   et al.
2017-04-27
SOI integrated circuit comprising adjacent cells of different types
Grant 9,190,334 - Thomas , et al. November 17, 2
2015-11-17
Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOS
Grant 9,099,354 - Weber , et al. August 4, 2
2015-08-04
Transistors With Various Levels Of Threshold Voltages And Absence Of Distortions Between Nmos And Pmos
App 20150041900 - Weber; Olivier ;   et al.
2015-02-12
Method Of Localized Modification Of The Stresses In A Substrate Of The Soi Type, In Particular Fd Soi Type, And Corresponding Device
App 20150021692 - Boeuf; Frederic ;   et al.
2015-01-22
Soi Integrated Circuit Comprising Adjacent Cells Of Different Types
App 20130065366 - Thomas; Olivier ;   et al.
2013-03-14
Shoe, particularly sport or leisure shoe
Grant 8,006,410 - Romboli , et al. August 30, 2
2011-08-30
Shoe, particularly sport or leisure shoe
App 20080244928 - Romboli; Sandra ;   et al.
2008-10-09

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