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Patent applications and USPTO patent grants for Warriner; Mark A..The latest application filed is for "method of speeding up output alignment in a digital phase locked loop".
Patent | Date |
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Method of speeding up output alignment in a digital phase locked loop Grant 10,069,503 - Zhang , et al. September 4, 2 | 2018-09-04 |
Method for improving the performance of synchronous serial interfaces Grant 10,002,090 - Warriner , et al. June 19, 2 | 2018-06-19 |
Low latency digital clock fault detector Grant 9,858,134 - Warriner , et al. January 2, 2 | 2018-01-02 |
Method Of Speeding Up Output Alignment In A Digital Phase Locked Loop App 20170346494 - Zhang; Changhui Cathy ;   et al. | 2017-11-30 |
Digital phase locked loop arrangement with master clock redundancy Grant 9,595,972 - Milijevic , et al. March 14, 2 | 2017-03-14 |
Method For Improving The Performance Of Synchronous Serial Interfaces App 20160299861 - Warriner; Mark A ;   et al. | 2016-10-13 |
A Low Latency Digital Clock Fault Detector App 20160299806 - Warriner; Mark A ;   et al. | 2016-10-13 |
Digital Phase Locked Loop Arrangement with Master Clock Redundancy App 20160301416 - Milijevic; Slobodan ;   et al. | 2016-10-13 |
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