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name:-0.014817953109741
name:-0.016412973403931
name:-0.0017058849334717
Warnock; James Douglas Patent Filings

Warnock; James Douglas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Warnock; James Douglas.The latest application filed is for "characterizing and simulating library gates to enable identification and elimination of electromigration violations in semicondu".

Company Profile
1.12.12
  • Warnock; James Douglas - Somers NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips
Grant 11,074,391 - Sigal , et al. July 27, 2
2021-07-27
Characterizing And Simulating Library Gates To Enable Identification And Elimination Of Electromigration Violations In Semicondu
App 20200233933 - Sigal; Leon ;   et al.
2020-07-23
Determining clock signal quality using a plurality of sensors
Grant 10,666,415 - Restle , et al.
2020-05-26
Determining clock signal quality using a plurality of sensors
Grant 10,652,006 - Restle , et al.
2020-05-12
Determining Clock Signal Quality Using A Plurality Of Sensors
App 20180198596 - Restle; Phillip John ;   et al.
2018-07-12
Determining Clock Signal Quality Using A Plurality Of Sensors
App 20180198595 - Restle; Phillip John ;   et al.
2018-07-12
LSSD compatibility for GSD unified global clock buffers
Grant 8,117,579 - Warnock , et al. February 14, 2
2012-02-14
Scan chain disable function for power saving
Grant 7,962,811 - Dhong , et al. June 14, 2
2011-06-14
Auto-tracking clock circuitry
App 20090160515 - Warnock; James Douglas
2009-06-25
Maintaining Circuit Delay Characteristics During Power Management Mode
App 20090121747 - Dhong; Sang Hoo ;   et al.
2009-05-14
Scan Chain Disable Function for Power Saving
App 20070061647 - Dhong; Sang Hoo ;   et al.
2007-03-15
Method of timing model abstraction for circuits containing simultaneously switching internal signals
Grant 7,191,419 - Soreff , et al. March 13, 2
2007-03-13
Scan chain disable function for power saving
Grant 7,165,006 - Dhong , et al. January 16, 2
2007-01-16
Scan chain disable function for power saving
App 20060095802 - Dhong; Sang Hoo ;   et al.
2006-05-04
Method of timing model abstraction for circuits containing simultaneously switching internal signals
App 20060031797 - Soreff; Jeffrey Paul ;   et al.
2006-02-09
Low skew, power efficient local clock signal generation system
Grant 6,927,615 - Dhong , et al. August 9, 2
2005-08-09
Method of power consumption reduction in clocked circuits
Grant 6,922,818 - Chu , et al. July 26, 2
2005-07-26
Enhanced debug scheme for LBIST
Grant 6,901,546 - Chu , et al. May 31, 2
2005-05-31
Low skew, power efficient local clock signal generation system
App 20040246037 - Dhong, Sang Hoo ;   et al.
2004-12-09
Unified Local Clock Buffer Structures
App 20040246027 - Dhong, Sang Hoo ;   et al.
2004-12-09
Unified local clock buffer structures
Grant 6,825,695 - Dhong , et al. November 30, 2
2004-11-30
Latching dynamic logic structure, and integrated circuit including same
Grant 6,744,282 - Dhong , et al. June 1, 2
2004-06-01
Enhanced debug scheme for LBIST
App 20020188903 - Chu, Sam Gat-Shang ;   et al.
2002-12-12
Method of power consumption reduction in clocked circuits
App 20020152409 - Chu, Sam Gat-Shang ;   et al.
2002-10-17

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