loadpatents
name:-0.025634765625
name:-0.027550935745239
name:-0.018033027648926
Ward; Kenneth L. Patent Filings

Ward; Kenneth L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ward; Kenneth L..The latest application filed is for "processor providing intelligent management of values buffered in overlaid architected and non-architected register files".

Company Profile
20.27.26
  • Ward; Kenneth L. - Austin TX
  • Ward; Kenneth L. - Machesney Park IL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Completion mechanism for a microprocessor instruction completion table
Grant 11,366,671 - Ward , et al. June 21, 2
2022-06-21
Processor providing intelligent management of values buffered in overlaid architected and non-architected register files
Grant 11,327,757 - Battle , et al. May 10, 2
2022-05-10
Finish status reporting for a simultaneous multithreading processor using an instruction completion table
Grant 11,269,647 - Ward , et al. March 8, 2
2022-03-08
Processor Providing Intelligent Management Of Values Buffered In Overlaid Architected And Non-architected Register Files
App 20210342150 - Battle; Steven J. ;   et al.
2021-11-04
Check pointing of accumulator register results in a microprocessor
Grant 11,119,772 - Battle , et al. September 14, 2
2021-09-14
Finish Exception Handling Of An Instruction Completion Table
App 20210271487 - Ward; Kenneth L. ;   et al.
2021-09-02
Finish exception handling of an instruction completion table
Grant 11,086,630 - Ward , et al. August 10, 2
2021-08-10
Prioritized instructions in an instruction completion table of a simultaneous multithreading processor
Grant 11,068,274 - Ward , et al. July 20, 2
2021-07-20
Check Pointing Of Accumulator Register Results In A Microprocessor
App 20210173649 - Battle; Steven J ;   et al.
2021-06-10
On-demand multi-tiered hang buster for SMT microprocessor
Grant 11,030,018 - Battle , et al. June 8, 2
2021-06-08
Instruction completion table with ready-to-complete vector
Grant 10,977,034 - Ward , et al. April 13, 2
2021-04-13
Speculatively releasing store data before store instruction completion in a processor
Grant 10,929,144 - Ward , et al. February 23, 2
2021-02-23
Speculative execution of both paths of a weakly predicted branch instruction
Grant 10,901,743 - Ward , et al. January 26, 2
2021-01-26
Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor
Grant 10,877,763 - Lloyd , et al. December 29, 2
2020-12-29
Most favored branch issue
Grant 10,831,492 - Ayub , et al. November 10, 2
2020-11-10
Mechanism for completing atomic instructions in a microprocessor
Grant 10,831,489 - Ward , et al. November 10, 2
2020-11-10
Instruction completion table containing entries that share instruction tags
Grant 10,761,856 - Ward , et al. Sep
2020-09-01
Speculatively Releasing Stores in a Processor
App 20200249946 - Kind Code
2020-08-06
Completion Mechanism For A Microprocessor Instruction Completion Table
App 20200241880 - WARD; Kenneth L. ;   et al.
2020-07-30
Completion mechanism for a microprocessor instruction completion table
Grant 10,725,786 - Ward , et al.
2020-07-28
Mechanism to stop completions using stop codes in an instruction completion table
Grant 10,713,057 - Ward , et al.
2020-07-14
Instruction Completion Table With Ready-to-complete Vector
App 20200142697 - Ward; Kenneth L. ;   et al.
2020-05-07
Mechanism To Stop Completions Using Stop Codes In An Instruction Completion Table
App 20200065110 - WARD; Kenneth L. ;   et al.
2020-02-27
Completion Mechanism For A Microprocessor Instruction Completion Table
App 20200065102 - WARD; Kenneth L. ;   et al.
2020-02-27
Mechanism For Completing Atomic Instructions In A Microprocessor
App 20200065103 - WARD; Kenneth L. ;   et al.
2020-02-27
Dispatching, Allocating, and Deallocating Instructions in a Queue in a Processor
App 20200042319 - Lloyd; Bryan ;   et al.
2020-02-06
Efficiently managing speculative finish tracking and error handling for load instructions
Grant 10,552,165 - Eisen , et al. Fe
2020-02-04
Instruction Completion Table Containing Entries That Share Instruction Tags
App 20200026521 - WARD; Kenneth L. ;   et al.
2020-01-23
Speculative Execution Of Both Paths Of A Weakly Predicted Branch Instruction
App 20200026520 - WARD; Kenneth L. ;   et al.
2020-01-23
Most Favored Branch Issue
App 20200012496 - Ayub; Salma ;   et al.
2020-01-09
Efficiently managing speculative finish tracking and error handling for load instructions
Grant 10,423,423 - Eisen , et al. Sept
2019-09-24
Finish Status Reporting For A Simultaneous Multithreading Processor Using An Instruction Completion Table
App 20190187993 - WARD; Kenneth L. ;   et al.
2019-06-20
Prioritized Instructions In An Instruction Completion Table Of A Simultaneous Multithreading Processor
App 20190187992 - WARD; Kenneth L. ;   et al.
2019-06-20
On-demand Multi-tiered Hang Buster For Smt Microprocessor
App 20190171569 - BATTLE; Steven J. ;   et al.
2019-06-06
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction
Grant 10,169,046 - Boersma , et al. J
2019-01-01
History buffer with single snoop tag for multiple-field registers
Grant 10,108,423 - Genden , et al. October 23, 2
2018-10-23
Universal history buffer to support multiple register types
Grant 9,996,353 - Genden , et al. June 12, 2
2018-06-12
History buffer for multiple-field registers
Grant 9,971,604 - Chadha , et al. May 15, 2
2018-05-15
Operation of a multi-slice processor with history buffers storing transaction memory state information
Grant 9,971,687 - Barrick , et al. May 15, 2
2018-05-15
Out-of-order Processor That Avoids Deadlock In Processing Queues By Designating A Most Favored Instruction
App 20180121205 - Boersma; Maarten J. ;   et al.
2018-05-03
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction
Grant 9,798,549 - Boersma , et al. October 24, 2
2017-10-24
Fpscr Sticky Bit Handling For Out Of Order Instruction Execution
App 20170300336 - BARRICK; BRIAN D. ;   et al.
2017-10-19
Operation Of A Multi-slice Processor With History Buffers Storing Transaction Memory State Information
App 20170235674 - BARRICK; BRIAN D. ;   et al.
2017-08-17
Efficiently Managing Speculative Finish Tracking And Error Handling For Load Instructions
App 20170090937 - EISEN; SUSAN E. ;   et al.
2017-03-30
Efficiently Managing Speculative Finish Tracking And Error Handling For Load Instructions
App 20170090941 - EISEN; SUSAN E. ;   et al.
2017-03-30
History Buffer with Single Snoop Tag for Multiple-Field Registers
App 20160283236 - Genden; Michael J. ;   et al.
2016-09-29
History Buffer for Multiple-Field Registers
App 20160253181 - Chadha; Sundeep ;   et al.
2016-09-01
Universal History Buffer to Support Multiple Register Types
App 20160253177 - Genden; Michael J. ;   et al.
2016-09-01
Method and apparatus to launch write queue read data in a microprocessor recovery unit
Grant 7,603,497 - Mack , et al. October 13, 2
2009-10-13
Method And Apparatus To Launch Write Queue Read Data In A Microprocessor Recovery Unit
App 20090132854 - Mack; Michael J. ;   et al.
2009-05-21
Method and apparatus to launch write queue read data in a microprocessor recovery unit
Grant 7,526,583 - Mack , et al. April 28, 2
2009-04-28
Method and apparatus to launch write queue read data in a microprocessor recovery unit
App 20070011516 - Mack; Michael J. ;   et al.
2007-01-11
Rail components for pick-up or flat-bed trucks to support side or back pieces
Grant 5,752,734 - Ward , et al. May 19, 1
1998-05-19

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