Ward, III; John W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ward, III; John W..The latest application filed is for "allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions".

Company Profile

0.9.6

Ward, III; John W. - Pflugerville TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions Grant 9,342,307 - Alexander , et al. May 17, 2	2016-05-17
Allocation Of Counters From A Pool Of Counters To Track Mappings Of Logical Registers To Physical Registers For Mapper Based Instruction Executions App 20140059329 - ALEXANDER; GREGORY W. ; et al.	2014-02-27
Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions Grant 8,661,230 - Alexander , et al. February 25, 2	2014-02-25
Allocation Of Counters From A Pool Of Counters To Track Mappings Of Logical Registers To Physical Registers For Mapper Based Instruction Executions App 20120265971 - ALEXANDER; GREGORY W. ; et al.	2012-10-18
Allocation Of Counters From A Pool Of Counters To Track Mappings Of Logical Registers To Physical Registers For Mapper Based Instruction Executions App 20120265969 - ALEXANDER; GREGORY W. ; et al.	2012-10-18
Methods, systems, and computer program products for recovering from branch prediction latency Grant 7,822,954 - Ward, III , et al. October 26, 2	2010-10-26
Dual-issuance of microprocessor instructions using dual dependency matrices Grant 7,769,984 - Alexander , et al. August 3, 2	2010-08-03
Dual-issuance Of Microprocessor Instructions Using Dual Dependency Matrices App 20100064121 - Alexander; Gregory W. ; et al.	2010-03-11
Method, System And Computer Program Product For Minimizing Branch Prediction Latency App 20090217017 - Alexander; Khary J. ; et al.	2009-08-27
Methods, Systems, And Computer Program Products For Recovering From Branch Prediction Latency App 20090210684 - Ward, III; John W. ; et al.	2009-08-20
Error detection enhancement in a microprocessor through the use of a second dependency matrix Grant 7,549,095 - Alexander , et al. June 16, 2	2009-06-16
Method for resource balancing using dispatch flush in a simultaneous multithread processor Grant 7,469,407 - Burky , et al. December 23, 2	2008-12-23
Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditions Grant 7,213,135 - Burky , et al. May 1, 2	2007-05-01
Method for managing power in a simultaneous multithread processor by loading instructions into pipeline circuit during select times based on clock signal frequency and selected power mode Grant 7,013,400 - Kalla , et al. March 14, 2	2006-03-14

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