Wann; Hsing-Jen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wann; Hsing-Jen.The latest application filed is for "selective silicon-on-insulator isolation structure and method".

Company Profile

0.12.7

Wann; Hsing-Jen - Fishkill NY
Wann; Hsing Jen - Carmel NY
Wann, Hsing-Jen - Briarcliff Manor NY
Wann; Hsing-Jen - Albany CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Selective silicon-on-insulator isolation structure and method Grant 7,923,786 - Steegen , et al. April 12, 2	2011-04-12
Selective Silicon-on-insulator Isolation Structure And Method App 20080029818 - Steegen; An L. ; et al.	2008-02-07
Selective silicon-on-insulator isolation structure and method Grant 7,326,983 - Steegen , et al. February 5, 2	2008-02-05
Reduced dielectric constant spacer materials integration for high speed logic gates Grant 7,081,393 - Belyansky , et al. July 25, 2	2006-07-25
Reduced Dielectric Constant Spacer Materials Integration For High Speed Logic Gates App 20050260819 - Belyansky, Michael P. ; et al.	2005-11-24
Selective silicon-on-insulator isolation structure and method Grant 6,936,522 - Steegen , et al. August 30, 2	2005-08-30
Selective silicon-on-insulator isolation structure and method App 20050164468 - Steegen, An L. ; et al.	2005-07-28
Selective Silicon-on-insulator Isolation Structure And Method App 20040262695 - Steegan, An L. ; et al.	2004-12-30
Structure and method of controlling short-channel effect of very short channel MOSFET App 20040033665 - Wann, Hsing-Jen	2004-02-19
Structure and method of controlling short-channel effect of very short channel MOSFET Grant 6,653,686 - Wann November 25, 2	2003-11-25
Patterned buried insulator App 20020072206 - Chen, Bomy A. ; et al.	2002-06-13
Structure And Method Of Controlling Short-channel Effect Of Very Short Channel Mosfet App 20020056873 - WANN, HSING-JEN	2002-05-16
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Grant 6,300,649 - Hu , et al. October 9, 2	2001-10-09
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Grant 6,121,077 - Hu , et al. September 19, 2	2000-09-19
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Grant 5,982,003 - Hu , et al. November 9, 1	1999-11-09
Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation Grant 5,780,899 - Hu , et al. July 14, 1	1998-07-14
Method of fabricating a self-aligned high speed MOSFET device Grant 5,599,728 - Hu , et al. February 4, 1	1997-02-04
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Grant 5,489,792 - Hu , et al. February 6, 1	1996-02-06
Capacitorless DRAM device on silicon-on-insulator substrate Grant 5,448,513 - Hu , et al. September 5, 1	1995-09-05

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