name:-0.0097160339355469
name:-0.0095460414886475
name:-0.0018360614776611
WANG; Youjun Patent Filings

WANG; Youjun

Patent Applications and Registrations

Patent applications and USPTO patent grants for WANG; Youjun.The latest application filed is for "video splitting method and electronic device".

Company Profile
1.9.8
  • WANG; Youjun - Shenzhen CN
  • Wang; Youjun - New Taipei TW
  • Wang; Youjun - New Taipei City TW
  • Wang; Youjun - Zhejiang CN
  • Wang; Youjun - Beijing CN
  • Wang; Youjun - Jiang Su Province CN
  • Wang; Youjun - Suzhou CN
  • Wang; Youjun - Jiangsu Province CN
  • Wang; Youjun - SuZhou Industrial Park CN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks
Patent Activity
PatentDate
Video Splitting Method And Electronic Device
App 20220021950 - WEI; Wenbo ;   et al.
2022-01-20
Test data integration system and method thereof
Grant 11,120,037 - Yang , et al. September 14, 2
2021-09-14
Test Data Integration System And Method Thereof
App 20200401596 - Yang; Yong ;   et al.
2020-12-24
Mixer
Grant D818,761 - Wang May 29, 2
2018-05-29
Mixer
Grant D818,764 - Wang May 29, 2
2018-05-29
Electrosurgical pencil
Grant D815,738 - Ye , et al. April 17, 2
2018-04-17
Method and device for processing geological information
Grant 9,256,981 - Shu , et al. February 9, 2
2016-02-09
Method and Device for Processing Geological Information
App 20140233809 - Shu; Bin ;   et al.
2014-08-21
Packaging structure
Grant 8,174,090 - Wang , et al. May 8, 2
2012-05-08
Optical Converter And Manufacturing Method Thereof And Light Emitting Diode
App 20100171134 - Shao; Mingda ;   et al.
2010-07-08
Packaging Method And Packaging Structure
App 20100133640 - Wang; Zhiqi ;   et al.
2010-06-03
Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same
Grant 7,663,213 - Yu , et al. February 16, 2
2010-02-16
Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same
Grant 7,394,152 - Yu , et al. July 1, 2
2008-07-01
Wafer Level Chip Size Packaged Chip Device With A Double-Layer Lead Structure And Method Of Fabricating The Same
App 20080111223 - Yu; Guoqing ;   et al.
2008-05-15
Wafer Level Chip Size Packaged Chip Device With An N-Shape Junction Inside And Method Of Fabricating The Same
App 20080111228 - Yu; Guoqing ;   et al.
2008-05-15

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed