Wang; Yen-Sen
Patent Applications and Registrations
Patent applications and USPTO patent grants for Wang; Yen-Sen.The latest application filed is for "integrated circuit layouts with fill feature shapes".
- Wang; Yen-Sen - Hsinchu City TW
- Wang; Yen-Sen - Hsinchu TW
- Wang; Yen-Sen - Hsinchu County TW
- Wang; Yen-Sen - Hsin-Chu N/A TW
| Patent | Date |
|---|---|
| Integrated Circuit Layouts with Fill Feature Shapes App 20220277128 - Yeh; Yu-Cheng ; et al. | 2022-09-01 |
| Integrated circuit layouts with fill feature shapes Grant 11,334,703 - Yeh , et al. May 17, 2 | 2022-05-17 |
| Semiconductor Structure And Method Of Forming The Same App 20210366824 - Chung; Shu-Wei ; et al. | 2021-11-25 |
| Charging prevention method and structure Grant 11,036,911 - Lin , et al. June 15, 2 | 2021-06-15 |
| Semiconductor Device App 20210125883 - Lin; Yen-Chun ; et al. | 2021-04-29 |
| Dummy Insertion Method App 20210100103 - Chung; Shu-Wei ; et al. | 2021-04-01 |
| Charging Prevention Method and Structure App 20210097228 - Lin; Han-Chung ; et al. | 2021-04-01 |
| Gate-All-Around Device with Different Channel Semiconductor Materials and Method of Forming the Same App 20210098310 - Lu; Jhe-Ching ; et al. | 2021-04-01 |
| Integrated Circuit Features with Obtuse Angles and Method of Forming Same App 20210074656 - Chung; Shu-Wei ; et al. | 2021-03-11 |
| Integrated circuit features with obtuse angles and method forming same Grant 10,861,807 - Chung , et al. December 8, 2 | 2020-12-08 |
| Integrated Circuit Features With Obtuse Angles and Method Forming Same App 20200161260 - Chung; Shu-Wei ; et al. | 2020-05-21 |
| Integrated Circuit Layouts with Fill Feature Shapes App 20190005180 - Yeh; Yu-Cheng ; et al. | 2019-01-03 |
| Semiconductor arrangement and formation thereof Grant 9,620,420 - Lu , et al. April 11, 2 | 2017-04-11 |
| Cut mask design layers to provide compact cell height Grant 9,551,923 - Wang , et al. January 24, 2 | 2017-01-24 |
| Semiconductor Arrangement And Formation Thereof App 20160268170 - Lu; Chen-Hung ; et al. | 2016-09-15 |
| Cell boundary layout Grant 9,405,879 - Wang , et al. August 2, 2 | 2016-08-02 |
| Semiconductor arrangement and formation thereof Grant 9,349,634 - Lu , et al. May 24, 2 | 2016-05-24 |
| Cut Mask Design Layers To Provide Compact Cell Height App 20150286765 - Wang; Yen-Sen ; et al. | 2015-10-08 |
| Cell Boundary Layout App 20150278428 - WANG; YEN-SEN ; et al. | 2015-10-01 |
| Semiconductor Arrangement And Formation Thereof App 20150243552 - Lu; Chen-Hung ; et al. | 2015-08-27 |
| Strain bars in stressed layers of MOS devices Grant 8,389,316 - Wang , et al. March 5, 2 | 2013-03-05 |
| Performance-aware logic operations for generating masks Grant 8,227,869 - Lu , et al. July 24, 2 | 2012-07-24 |
| Performance-Aware Logic Operations for Generating Masks App 20120043618 - Lu; Lee-Chung ; et al. | 2012-02-23 |
| Performance-aware logic operations for generating masks Grant 8,122,394 - Lu , et al. February 21, 2 | 2012-02-21 |
| Strain Bars in Stressed Layers of MOS Devices App 20110195554 - Wang; Yen-Sen ; et al. | 2011-08-11 |
| Strain bars in stressed layers of MOS devices Grant 7,943,961 - Wang , et al. May 17, 2 | 2011-05-17 |
| Performance-Aware Logic Operations for Generating Masks App 20100065913 - Lu; Lee-Chung ; et al. | 2010-03-18 |
| Strain Bars in Stressed Layers of MOS Devices App 20090230439 - Wang; Yen-Sen ; et al. | 2009-09-17 |
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