loadpatents
name:-0.013936996459961
name:-0.022522926330566
name:-0.0024831295013428
Wang; Wen-Hann Patent Filings

Wang; Wen-Hann

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wang; Wen-Hann.The latest application filed is for "scalable distributed memory and i/o multiprocessor system".

Company Profile
0.20.8
  • Wang; Wen-Hann - Portland OR
  • Wang; Wen-Hann - Shanghai CN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Scalable distributed memory and I/O multiprocessor system
Grant 8,745,306 - Rankin , et al. June 3, 2
2014-06-03
Scalable Distributed Memory And I/o Multiprocessor System
App 20120317328 - Rankin; Linda J. ;   et al.
2012-12-13
Scalable distributed memory and I/O multiprocessor system
Grant 8,255,605 - Rankin , et al. August 28, 2
2012-08-28
Scalable Distributed Memory And I/o Multiprocessor System
App 20110185101 - Rankin; Linda J. ;   et al.
2011-07-28
Scalable memory and I/O multiprocessor systems
Grant 7,930,464 - Rankin , et al. April 19, 2
2011-04-19
Scalable Distributed Memory And I/o Multiprocessor Systems And Associated Methods
App 20090319717 - Rankin; Linda J. ;   et al.
2009-12-24
Scalable distributed memory and I/O multiprocessor systems and associated methods
Grant 7,603,508 - Rankin , et al. October 13, 2
2009-10-13
Scalable Distributed Memory And I/o Multiprocessor Systems And Associated Methods
App 20080114919 - Rankin; Linda J. ;   et al.
2008-05-15
Scalable distributed memory and I/O multiprocessor systems and associated methods
Grant 7,343,442 - Rankin , et al. March 11, 2
2008-03-11
Scalable distributed memory and I/O multiprocessor systems and associated methods
App 20070106833 - Rankin; Linda J. ;   et al.
2007-05-10
Cache line pre-load and pre-own based on cache coherence speculation
Grant 7,076,613 - Peir , et al. July 11, 2
2006-07-11
Scalable distributed memory and I/O multiprocessor system
Grant 7,058,750 - Rankin , et al. June 6, 2
2006-06-06
Cache line pre-load and pre-own based on cache coherence speculation
App 20040268054 - Peir, Jih-Kwon ;   et al.
2004-12-30
Cache line pre-load and pre-own based on cache coherence speculation
Grant 6,725,341 - Peir , et al. April 20, 2
2004-04-20
Hardware assisted dynamic optimization of program execution
App 20030005423 - Chen, Dong-Yuan ;   et al.
2003-01-02
Configurable system monitoring for dynamic optimization of program execution
App 20030004974 - Wang, Hong ;   et al.
2003-01-02
Apparatus and method for caching lock conditions in a multi-processor system
Grant 6,006,299 - Wang , et al. December 21, 1
1999-12-21
Computer system having tag information in a processor and cache memory
Grant 5,956,746 - Wang September 21, 1
1999-09-21
Backward inquiry to lower level caches prior to the eviction of a modified line from a higher level cache in a microprocessor hierarchical cache structure
Grant 5,829,038 - Merrell , et al. October 27, 1
1998-10-27
Method and apparatus for cache memory replacement line identification
Grant 5,809,524 - Singh , et al. September 15, 1
1998-09-15
Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system
Grant 5,715,428 - Wang , et al. February 3, 1
1998-02-03
Method and apparatus for transferring information between a processor and a memory system
Grant 5,701,503 - Singh , et al. December 23, 1
1997-12-23
Cache memory with reduced request-blocking
Grant 5,642,494 - Wang , et al. June 24, 1
1997-06-24
Virtual access cache protection bits handling method and apparatus
Grant 5,619,673 - Wang April 8, 1
1997-04-08
Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches
Grant 5,551,005 - Sarangdhar , et al. August 27, 1
1996-08-27
Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory
Grant 5,548,742 - Wang , et al. August 20, 1
1996-08-20
System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
Grant 5,530,832 - So , et al. June 25, 1
1996-06-25

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed