| Patent | Date |
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Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
Grant 11,404,405 - Wang , et al. August 2, 2 | 2022-08-02 |
Method Of Forming Multiple-vt Fets For Cmos Circuit Applications
App 20210376109 - Wang; Wei-E ; et al. | 2021-12-02 |
Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding
Grant 11,189,600 - Wang , et al. November 30, 2 | 2021-11-30 |
Method of forming isolation dielectrics for stacked field effect transistors (FETs)
Grant 11,158,738 - Wang , et al. October 26, 2 | 2021-10-26 |
Method of forming multiple-Vt FETs for CMOS circuit applications
Grant 11,088,258 - Wang , et al. August 10, 2 | 2021-08-10 |
Metal oxide semiconductor field effect transistor with crystalline oxide layer on a III-V material
Grant 11,081,590 - Wang , et al. August 3, 2 | 2021-08-03 |
Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
Grant 11,069,576 - Wang July 20, 2 | 2021-07-20 |
Method Of Forming Sacrificial Self-aligned Features For Assisting Die-to-die And Die-to-wafer Direct Bonding
App 20210183814 - Wang; Wei-E ; et al. | 2021-06-17 |
Method Of Forming A Thermal Shield In A Monolithic 3-d Integrated Circuit
App 20210183729 - Wang; Wei-E ; et al. | 2021-06-17 |
Method of forming a thermal shield in a monolithic 3-D integrated circuit
Grant 10,971,420 - Wang , et al. April 6, 2 | 2021-04-06 |
Method Of Forming Isolation Dielectrics For Stacked Field Effect Transistors (fets)
App 20200403097 - WANG; Wei-E ; et al. | 2020-12-24 |
Semiconductor Device Including A Repeater/buffer At Upper Metal Routing Layers And Methods Of Manufacturing The Same
App 20200381414 - Wang; Wei-E ; et al. | 2020-12-03 |
Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
Grant 10,854,591 - Wang , et al. December 1, 2 | 2020-12-01 |
Method Of Forming Multi-threshold Voltage Devices Using Dipole-high Dielectric Constant Combinations And Devices So Formed
App 20200357700 - Wang; Wei-E | 2020-11-12 |
Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
Grant 10,770,353 - Wang Sep | 2020-09-08 |
Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same
Grant 10,727,297 - Wang , et al. | 2020-07-28 |
Method Of Forming A Thermal Shield In A Monolithic 3-d Integrated Circuit
App 20200203247 - Wang; Wei-E ; et al. | 2020-06-25 |
Method Of Forming Multiple-vt Fets For Cmos Circuit Applications
App 20200194569 - Wang; Wei-E ; et al. | 2020-06-18 |
Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed
Grant 10,586,738 - Wang , et al. | 2020-03-10 |
Method Of Forming Crystalline Oxides On Iii-v Materials
App 20200035838 - Wang; Wei-E ; et al. | 2020-01-30 |
Method Of Forming Multi-threshold Voltage Devices And Devices So Formed
App 20190385856 - Wang; Wei-E ; et al. | 2019-12-19 |
Method of forming crystalline oxides on III-V materials
Grant 10,475,930 - Wang , et al. Nov | 2019-11-12 |
Method of forming multi-threshold voltage devices and devices so formed
Grant 10,446,400 - Wang , et al. Oc | 2019-10-15 |
Method Of Forming Multi-threshold Voltage Devices Using Dipole-high Dielectric Constant Combinations And Devices So Formed
App 20190148237 - Wang; Wei-E | 2019-05-16 |
Method Of Providing Source And Drain Doping For Cmos Architecture Including Finfet And Semiconductor Devices So Formed
App 20190131182 - Wang; Wei-E ; et al. | 2019-05-02 |
Method Of Forming Multi-threshold Voltage Devices And Devices So Formed
App 20190122891 - Wang; Wei-E ; et al. | 2019-04-25 |
Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same
Grant 10,026,751 - Rakshit , et al. July 17, 2 | 2018-07-17 |
Horizontal nanosheet FETs and method of manufacturing the same
Grant 10,026,652 - Wang , et al. July 17, 2 | 2018-07-17 |
Semiconductor Device Including A Repeater/buffer At Upper Metal Routing Layers And Methods Of Manufacturing The Same
App 20180130785 - Wang; Wei-E ; et al. | 2018-05-10 |
Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same
Grant 9,941,405 - Kittl , et al. April 10, 2 | 2018-04-10 |
Complimentary Metal-oxide-semiconductor Circuit Having Transistors With Different Threshold Voltages And Method Of Manufacturing The Same
App 20180076199 - Wang; Wei-E ; et al. | 2018-03-15 |
Method of forming internal dielectric spacers for horizontal nanosheet FET architectures
Grant 9,905,672 - Wang , et al. February 27, 2 | 2018-02-27 |
Horizontal Nanosheet Fets And Method Of Manufacturing The Same
App 20180053690 - Wang; Wei-E ; et al. | 2018-02-22 |
Method Of Forming Crystalline Oxides On Iii-v Materials
App 20180053859 - Wang; Wei-E ; et al. | 2018-02-22 |
Methods of forming nanosheets on lattice mismatched substrates
Grant 9,870,940 - Wang , et al. January 16, 2 | 2018-01-16 |
Method Of Forming Internal Dielectric Spacers For Horizontal Nanosheet Fet Architectures
App 20170338328 - WANG; Wei-E ; et al. | 2017-11-23 |
Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance
Grant 9,812,449 - Obradovic , et al. November 7, 2 | 2017-11-07 |
Multi-layer fin field effect transistor devices and methods of forming the same
Grant 9,793,403 - Obradovic , et al. October 17, 2 | 2017-10-17 |
Relaxed semiconductor layers with reduced defects and methods of forming the same
Grant 9,773,906 - Wang , et al. September 26, 2 | 2017-09-26 |
Nanosheet And Nanowire Devices Having Source/drain Stressors And Methods Of Manufacturing The Same
App 20170271514 - Kittl; Jorge A. ; et al. | 2017-09-21 |
Interface layer for gate stack using O.sub.3 post treatment
Grant 9,698,234 - Kittl , et al. July 4, 2 | 2017-07-04 |
Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators
Grant 9,691,860 - Wang , et al. June 27, 2 | 2017-06-27 |
Multi-vt Gate Stack For Iii-v Nanosheet Devices With Reduced Parasitic Capacitance
App 20170148787 - Obradovic; Borna J. ; et al. | 2017-05-25 |
Semiconductor Device Including A Repeater/buffer At Higher Metal Routing Layers And Methods Of Manufacturing The Same
App 20170098661 - Rakshit; Titash ; et al. | 2017-04-06 |
Methods of Forming Nanosheets on Lattice Mismatched Substrates
App 20170040209 - Wang; Wei-E ; et al. | 2017-02-09 |
Relaxed Semiconductor Layers With Reduced Defects and Methods of Forming the Same
App 20160322493 - Wang; Wei-E ; et al. | 2016-11-03 |
Multi-layer Fin Field Effect Transistor Devices And Methods Of Forming The Same
App 20160308055 - OBRADOVIC; BORNA J. ; et al. | 2016-10-20 |
Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
Grant 9,343,303 - Wang , et al. May 17, 2 | 2016-05-17 |
Rectangular Nanosheet Fabrication
App 20160071729 - Hatcher; Ryan M. ; et al. | 2016-03-10 |
Interface Layer For Gate Stack Using 03 Post Treatment
App 20160042956 - Kittl; Jorge A. ; et al. | 2016-02-11 |
Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof
Grant 9,218,964 - Wang , et al. December 22, 2 | 2015-12-22 |
Methods Of Forming Defect-free Srb Onto Lattice-mismatched Substrates And Defect-free Fins On Insulators
App 20150318355 - WANG; Wei-E ; et al. | 2015-11-05 |
Methods Of Forming Low-defect Strain-relaxed Layers On Lattice-mismatched Substrates And Related Semiconductor Structures And Devices
App 20150270120 - Wang; Wei-E ; et al. | 2015-09-24 |
Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods
Grant 9,064,699 - Wang , et al. June 23, 2 | 2015-06-23 |
Methods Of Forming Semiconductor Patterns Including Reduced Dislocation Defects And Devices Formed Using Such Methods
App 20150093884 - Wang; Wei-E ; et al. | 2015-04-02 |
Gated Circuit Structure With Ultra-thin, Epitaxially-grown Tunnel And Channel Layer
App 20140054549 - LOH; Wei-Yip ; et al. | 2014-02-27 |
Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device
Grant 8,524,562 - Wang , et al. September 3, 2 | 2013-09-03 |
Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof
App 20130154112 - Zhang; Wenqi ; et al. | 2013-06-20 |
Antiphase Domain Boundary-Free III-V Compound Semiconductor Material on Semiconductor Substrate and Method for Manufacturing Thereof
App 20120032234 - Wang; Gang ; et al. | 2012-02-09 |
Method For Reducing Fermi-level-pinning In A Non-silicon Channel Mos Device
App 20100065824 - Wang; Wei-E ; et al. | 2010-03-18 |
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