Wang; Tsing-Chow

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wang; Tsing-Chow.The latest application filed is for "package structure of optical transceiver component".

Company Profile

0.24.15

Wang; Tsing-Chow - Zhongli TW
WANG; Tsing-Chow - Zhongli City TW
Wang; Tsing-Chow - Kaohsiung N/A TW
Wang; Tsing-Chow - Kaohsiung City TW
WANG; Tsing Chow - Shanghai CN
Wang; Tsing-Chow - Cupertino CA
Wang; Tsing-Chow - San Jose CA
Wang; Tsing-Chow - Norristown PA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Package structure of optical transceiver component Grant 9,129,883 - Huang , et al. September 8, 2	2015-09-08
Package Structure Of Optical Transceiver Component App 20140239315 - HUANG; Yun-Cheng ; et al.	2014-08-28
Optical transceiver module Grant 8,721,194 - Huang , et al. May 13, 2	2014-05-13
Optical Transceiver Module App 20130287406 - HUANG; Yun-Cheng ; et al.	2013-10-31
Bga Package Structure And Method For Fabricating The Same App 20120153470 - WANG; Tsing Chow	2012-06-21
Multi-die semiconductor package structure and method for manufacturing the same Grant 7,875,505 - Wang January 25, 2	2011-01-25
Fluxless reflow process for bump formation Grant 7,838,411 - Wang , et al. November 23, 2	2010-11-23
Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes Grant 7,816,787 - Wang October 19, 2	2010-10-19
Lead Frame App 20090289337 - Wang; Tsing Chow	2009-11-26
Method of Forming Low Stress Multi-Layer Metallurgical Structures and High Reliable Lead Free Solder Termination Electrodes App 20090072396 - Wang; Tsing Chow	2009-03-19
Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes Grant 7,462,556 - Wang December 9, 2	2008-12-09
Lead Frame App 20080157307 - WANG; Tsing Chow	2008-07-03
Multi-Die Semiconductor Package Structure and Method for Manufacturing the Same App 20080157308 - Wang; Tsing-Chow	2008-07-03
Method for Fabricating Semiconductor Device App 20080153240 - WANG; Tsing Chow ; et al.	2008-06-26
Fluxless Reflow Process for Bump Formation App 20080128476 - Wang; Tsing-Chow ; et al.	2008-06-05
Planar bond pad design and method of making the same Grant 7,381,636 - Wang June 3, 2	2008-06-03
Planar bond pad design and method of making the same App 20070023926 - Wang; Tsing Chow	2007-02-01
Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes App 20060234489 - Wang; Tsing Chow	2006-10-19
Planar bond pad design and method of making the same Grant 7,053,490 - Wang May 30, 2	2006-05-30
Flat-top bumping structure and preparation method Grant 6,784,089 - Lei , et al. August 31, 2	2004-08-31
Flat-top Bumping Structure And Preparation Method App 20040137707 - Lei, Kuolung ; et al.	2004-07-15
Stacked paired die package and method of making the same Grant 6,674,173 - Wang January 6, 2	2004-01-06
Method for forming patterned polyimide layer Grant 6,635,585 - Khe , et al. October 21, 2	2003-10-21
Microelectronic Fabrication Having Formed Therein Terminal Electrode Structure Providing Enhanced Barrier Properties App 20030049924 - Wang, Tsing-Chow	2003-03-13
Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball Grant 6,424,037 - Ho , et al. July 23, 2	2002-07-23
Method for fabricating a microelectronic fabrication having formed therein a redistribution structure Grant 6,362,087 - Wang , et al. March 26, 2	2002-03-26
Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball App 20020025599 - Ho, Chung W. ; et al.	2002-02-28
Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties Grant 6,316,831 - Wang November 13, 2	2001-11-13
Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball Grant 6,281,041 - Ho , et al. August 28, 2	2001-08-28
Bump formation on yielded semiconductor dies Grant 5,587,336 - Wang , et al. December 24, 1	1996-12-24
Semi-conductor device interconnect package assembly for improved package performance Grant 5,414,299 - Wang , et al. May 9, 1	1995-05-09
Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrate Grant 5,171,712 - Wang , et al. December 15, 1	1992-12-15
High density Josephson junction memory circuit Grant 4,509,146 - Wang , et al. April 2, 1	1985-04-02
Josephson junction latch circuit Grant 4,501,975 - Josephs , et al. February 26, 1	1985-02-26
High gain Josephson junction voltage amplifier Grant 4,458,160 - Josephs , et al. July 3, 1	1984-07-03
Method of making improved tunnel barriers for superconducting Josephson junction devices Grant 4,437,227 - Flannery , et al. March 20, 1	1984-03-20
Three Josephson junction direct coupled isolation circuit Grant 4,413,196 - Josephs , et al. November 1, 1	1983-11-01

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