name:-0.023255825042725
name:-0.023705005645752
name:-0.0227370262146
Wang; Shao-Huan Patent Filings

Wang; Shao-Huan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wang; Shao-Huan.The latest application filed is for "integrated circuit and method of forming same and a system".

Company Profile
21.19.22
  • Wang; Shao-Huan - Hsinchu TW
  • Wang; Shao-huan - Taichung TW
  • WANG; Shao-Huan - Taichung City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks
Patent Activity
PatentDate
Method of designing semiconductor device
Grant 11,449,656 - Wang , et al. September 20, 2
2022-09-20
Integrated circuit having a high cell density
Grant 11,437,319 - Chen , et al. September 6, 2
2022-09-06
Integrated Circuit And Method Of Forming Same And A System
App 20220198122 - CHEN; Sheng-Hsiung ;   et al.
2022-06-23
Integrated circuit and method of forming same and a system
Grant 11,275,886 - Chen , et al. March 15, 2
2022-03-15
Standard Cells And Variations Thereof Within A Standard Cell Library
App 20220067266 - CHEN; Sheng-Hsiung ;   et al.
2022-03-03
Circuit Layouts And Related Methods
App 20220035982 - LIN; CHIN-SHEN ;   et al.
2022-02-03
Standard cells and variations thereof within a standard cell library
Grant 11,182,533 - Chen , et al. November 23, 2
2021-11-23
Placement constraint method for multiple patterning of cell-based chip design
Grant 11,170,149 - Wang , et al. November 9, 2
2021-11-09
Integrated Circuit And Method Of Forming Same And A System
App 20210256193 - CHEN; Sheng-Hsiung ;   et al.
2021-08-19
Systems And Methods For Integrated Circuit Layout
App 20210224456 - Chen; Sheng-Hsiung ;   et al.
2021-07-22
Integrated device and method of forming the same
Grant 11,030,383 - Ku , et al. June 8, 2
2021-06-08
Integrated circuit and method of forming same and a system
Grant 10,990,745 - Chen , et al. April 27, 2
2021-04-27
Logic Cell Structure And Integrated Circuit With The Logic Cell Structure
App 20210091769 - WANG; SHAO-HUAN ;   et al.
2021-03-25
Integrated Circuit Having a High Cell Density
App 20210028108 - Chen; Sheng-Hsiung ;   et al.
2021-01-28
Method Of Designing Semiconductor Device
App 20210004517 - WANG; Shao-Huan ;   et al.
2021-01-07
Logic cell structure and integrated circuit with the logic cell structure
Grant 10,868,538 - Wang , et al. December 15, 2
2020-12-15
Method of designing semiconductor device and system for implementing the method
Grant 10,817,643 - Wang , et al. October 27, 2
2020-10-27
Standard Cells And Variations Thereof Within A Standard Cell Library
App 20200328202 - CHEN; Sheng-Hsiung ;   et al.
2020-10-15
Integrated circuit having a high cell density
Grant 10,804,200 - Chen , et al. October 13, 2
2020-10-13
Integrated Device And Method Of Forming The Same
App 20200285798 - KU; CHUN-YAO ;   et al.
2020-09-10
Standard cells and variations thereof within a standard cell library
Grant 10,741,539 - Chen , et al. A
2020-08-11
Integrated device and method of forming the same
Grant 10,678,991 - Ku , et al.
2020-06-09
Integrated Circuit And Method Of Forming Same And A System
App 20200097634 - CHEN; Sheng-Hsiung ;   et al.
2020-03-26
Placement Constraint Method for Multiple Patterning of Cell-Based Chip Design
App 20200089840 - WANG; Shao-Huan ;   et al.
2020-03-19
Integrated Device And Method Of Forming The Same
App 20200004917 - KU; CHUN-YAO ;   et al.
2020-01-02
Placement constraint method for multiple patterning of cell-based chip design
Grant 10,521,545 - Wang , et al. Dec
2019-12-31
Must-join pin sign-off method
Grant 10,509,887 - Chen , et al. Dec
2019-12-17
Method Of Designing Semiconductor Device And System For Implementing The Method
App 20190266309 - WANG; Shao-Huan ;   et al.
2019-08-29
Circuit with combined cells and method for manufacturing the same
Grant 10,396,063 - Chang , et al. A
2019-08-27
Must-Join Pin Sign-Off Method
App 20190155983 - CHEN; Sheng-Hsiung ;   et al.
2019-05-23
Layout for semiconductor device including via pillar structure
Grant 10,289,794 - Wang , et al.
2019-05-14
Integrated Circuit Having a High Cell Density
App 20190096805 - Chen; Sheng-Hsiung ;   et al.
2019-03-28
Standard Cells and Variations Thereof Within a Standard Cell Library
App 20190064770 - CHEN; Sheng-Hsiung ;   et al.
2019-02-28
Integrated circuit having a high cell density
Grant 10,157,840 - Chen , et al. Dec
2018-12-18
Layout For Semiconductor Device Including Via Pillar Structure
App 20180165403 - WANG; Shao-Huan ;   et al.
2018-06-14
Systems and methods for generating a multiple patterning lithography compliant integrated circuit layout
Grant 9,996,657 - Chen , et al. June 12, 2
2018-06-12
Integrated Circuit Having a High Cell Density
App 20180158776 - Chen; Sheng-Hsiung ;   et al.
2018-06-07
Method and circuit for via pillar optimization
Grant 9,977,857 - Ku , et al. May 22, 2
2018-05-22
Systems and Methods for Generating a Multiple Patterning Lithography Compliant Integrated Circuit Layout
App 20180032661 - Chen; Chun-Chen ;   et al.
2018-02-01
Circuit With Combined Cells And Method For Manufacturing The Same
App 20170345809 - CHANG; FONG-YUAN ;   et al.
2017-11-30
Placement Constraint Method for Multiple Patterning of Cell-Based Chip Design
App 20170300610 - Wang; Shao-Huan ;   et al.
2017-10-19

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed