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name:-0.055884122848511
name:-0.043413877487183
name:-0.00073099136352539
Wang; Laung-Terng Patent Filings

Wang; Laung-Terng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wang; Laung-Terng.The latest application filed is for "multiple-capture dft method for detecting or locating crossing clock-domain faults during self-test or scan-test".

Company Profile
0.44.50
  • Wang; Laung-Terng - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 9,696,377 - Wang , et al. July 4, 2
2017-07-04
Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 9,678,156 - Wang , et al. June 13, 2
2017-06-13
Multiple-capture Dft Method For Detecting Or Locating Crossing Clock-domain Faults During Self-test Or Scan-test
App 20160131707 - Wang; Laung-Terng ;   et al.
2016-05-12
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
Grant 9,316,688 - Wang , et al. April 19, 2
2016-04-19
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
Grant 9,274,168 - Wang , et al. March 1, 2
2016-03-01
Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit
App 20150338461 - Wang; Laung-Terng ;   et al.
2015-11-26
Multiple-capture Dft System For Detecting Or Locating Crossing Clock-domain Faults During Scan-test
App 20150338465 - WANG; Laung-Terng ;   et al.
2015-11-26
Multiple-capture Dft System For Detecting Or Locating Crossing Clock-domain Faults During Scan-test
App 20150316616 - WANG; LAUNG-TERNG ;   et al.
2015-11-05
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 9,121,902 - Wang , et al. September 1, 2
2015-09-01
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 9,110,139 - Wang , et al. August 18, 2
2015-08-18
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
Grant 9,091,730 - Wang , et al. July 28, 2
2015-07-28
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 9,057,763 - Wang , et al. June 16, 2
2015-06-16
Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
Grant 9,046,572 - Wang , et al. June 2, 2
2015-06-02
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 9,026,875 - Wang , et al. May 5, 2
2015-05-05
Method and apparatus for hybrid ring generator design
Grant 8,949,299 - Wang , et al. February 3, 2
2015-02-03
Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit
App 20140344636 - Wang; Laung-Terng ;   et al.
2014-11-20
Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Scan-Test
App 20140223251 - Wang; Laung-Terng ;   et al.
2014-08-07
Computer-aided design system to automate scan synthesis at register-transfer level
Grant 8,775,985 - Wang , et al. July 8, 2
2014-07-08
Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit
App 20140149816 - Wang; Laung-Terng ;   et al.
2014-05-29
Method And Apparatus For Low-pin-count Scan Compression
App 20140143623 - TOUBA; Nur A. ;   et al.
2014-05-22
Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test
App 20140082446 - Wang; Laung-Terng ;   et al.
2014-03-20
Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test
App 20140075256 - Wang; Laung-Terng ;   et al.
2014-03-13
Computer-Aided Design (CAD) Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults
App 20140075257 - Wang; Laung-Terng ;   et al.
2014-03-13
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 8,667,451 - Wang March 4, 2
2014-03-04
X-Tracer: A Reconfigurable X-Tolerance Trace Compressor for Silicon Debug
App 20130326281 - Xu; Qiang ;   et al.
2013-12-05
Method for Unified High-Level Hardware Description Language Simulation Based on Parallel Computing Platforms
App 20130304450 - Tsai; Tso-Sheng ;   et al.
2013-11-14
Computer-aided Design System To Automate Scan Synthesis At Register-transfer Level
App 20130305200 - WANG; Laung-Terng ;   et al.
2013-11-14
Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test
App 20130268818 - Wang; Laung-Terng ;   et al.
2013-10-10
Method and apparatus for testing 3D integrated circuits
Grant 8,522,096 - Wang , et al. August 27, 2
2013-08-27
Multiple-capture DFT system to reduce peak capture power during self-test or scan test
Grant 8,458,544 - Wang , et al. June 4, 2
2013-06-04
Robust scan synthesis for protecting soft errors
Grant 8,418,100 - Wang , et al. April 9, 2
2013-04-09
Apparatus and method for protecting soft errors
Grant 8,402,328 - Wang , et al. March 19, 2
2013-03-19
Method And Apparatus For Hybrid Ring Generator Design
App 20130036146 - Wang; Laung-Terng ;   et al.
2013-02-07
Method and apparatus for low-pin-count scan compression
Grant 8,335,954 - Touba , et al. December 18, 2
2012-12-18
Method And Apparatus For Low-pin-count Scan Compression
App 20120266036 - TOUBA; Nur A. ;   et al.
2012-10-18
Method and apparatus for low-pin-count scan compression
Grant 8,230,282 - Touba , et al. July 24, 2
2012-07-24
Computer-aided design system to automate scan synthesis at register-transfer level
Grant 8,219,945 - Wang , et al. July 10, 2
2012-07-10
Robust Scan Synthesis For Protecting Soft Errors
App 20120173940 - WANG; Laung-Terng ;   et al.
2012-07-05
Multiple-capture Dft System To Reduce Peak Capture Power During Self-test Or Scan Test
App 20120166903 - WANG; Laung-Terng ;   et al.
2012-06-28
Method And Apparatus For Testing 3d Integrated Circuits
App 20120110402 - Wang; Laung-Terng ;   et al.
2012-05-03
Robust scan synthesis for protecting soft errors
Grant 8,161,441 - Wang , et al. April 17, 2
2012-04-17
Multiple-capture DFT system to reduce peak capture power during self-test or scan test
Grant 8,091,002 - Wang , et al. January 3, 2
2012-01-03
Method And Apparatus For Low-pin-count Scan Compression
App 20110258501 - TOUBA; Nur A. ;   et al.
2011-10-20
Method and apparatus for low-pin-count scan compression
Grant 7,996,741 - Touba , et al. August 9, 2
2011-08-09
Computer-aided design system to automate scan synthesis at register-transfer level
Grant 7,904,857 - Wang , et al. March 8, 2
2011-03-08
Method And Apparatus For Low-pin-count Scan Compression
App 20110047426 - TOUBA; Nur A. ;   et al.
2011-02-24
Apparatus And Method For Protecting Soft Errors
App 20110022909 - WANG; Laung-Terng ;   et al.
2011-01-27
FPGA Test Configuration Minimization
App 20110022907 - Jiang; Zhigang ;   et al.
2011-01-27
Robust Scan Synthesis For Protecting Soft Errors
App 20110022908 - WANG; Laung-Terng ;   et al.
2011-01-27
Multiple-capture Dft System To Reduce Peak Capture Power During Self-test Or Scan Test
App 20100287430 - WANG; Laung-Terng ;   et al.
2010-11-11
Apparatus for redundancy reconfiguration of faculty memories
Grant 7,783,940 - Yu , et al. August 24, 2
2010-08-24
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 7,779,323 - Wang , et al. August 17, 2
2010-08-17
Method and apparatus for unifying self-test with scan-test during prototype debug and production test
Grant 7,747,920 - Wang , et al. June 29, 2
2010-06-29
Method And Apparatus For Delay Fault Coverage Enhancement
App 20100138709 - WANG; Laung-Terng ;   et al.
2010-06-03
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 7,721,173 - Wang , et al. May 18, 2
2010-05-18
Apparatus for redundancy reconfiguration of faculty memories
App 20090303815 - Yu; Lizhen ;   et al.
2009-12-10
Method And Apparatus For Broadcasting Scan Patterns In A Scan-based Integrated Circuit
App 20090235132 - Wang; Laung-Terng ;   et al.
2009-09-17
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 7,552,373 - Wang , et al. June 23, 2
2009-06-23
Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
Grant 7,512,851 - Wang , et al. March 31, 2
2009-03-31
Method and apparatus for unifying self-test with scan-test during prototype debug and production test
App 20090037786 - Wang; Laung-Terng ;   et al.
2009-02-05
Multiple-capture DFT system for scan-based integrated circuits
Grant 7,451,371 - Wang , et al. November 11, 2
2008-11-11
Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
Grant 7,434,126 - Wang , et al. October 7, 2
2008-10-07
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 7,412,672 - Wang , et al. August 12, 2
2008-08-12
Computer-aided design system to automate scan synthesis at register-transfer level
App 20080134107 - Wang; Laung-Terng ;   et al.
2008-06-05
Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
App 20070255988 - Wang; Laung-Terng ;   et al.
2007-11-01
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
Grant 7,284,175 - Wang , et al. October 16, 2
2007-10-16
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
Grant 7,260,756 - Wang , et al. August 21, 2
2007-08-21
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
App 20070168803 - Wang; Laung-Terng ;   et al.
2007-07-19
Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
Grant 7,124,342 - Wang , et al. October 17, 2
2006-10-17
Mask network design for scan-based integrated circuits
App 20060156122 - Wang; Laung-Terng ;   et al.
2006-07-13
Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
Grant 7,058,869 - Abdel-Hafez , et al. June 6, 2
2006-06-06
IEEE Std. 1149.4 compatible analog BIST methodology
App 20060059395 - Su; Chauchin ;   et al.
2006-03-16
Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
App 20050262409 - Wang, Laung-Terng ;   et al.
2005-11-24
Multiple-capture DFT system for scan-based integrated circuits
App 20050235186 - Wang, Laung-Terng ;   et al.
2005-10-20
Computer-aided design system to automate scan synthesis at register-transfer level
Grant 6,957,403 - Wang , et al. October 18, 2
2005-10-18
Computer-aided design system to automate scan synthesis at register-transfer level
App 20050229123 - Wang, Laung-Terng ;   et al.
2005-10-13
Mask network design for scan-based integrated circuits
App 20050060625 - Wang, Laung-Terng ;   et al.
2005-03-17
Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
App 20050055617 - Wang, Laung-Terng ;   et al.
2005-03-10
Method and apparatus for unifying self-test with scan-test during prototype debug and production test
App 20040268181 - Wang, Laung-Terng ;   et al.
2004-12-30
Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
App 20040237015 - Abdel-Hafez, Khader S. ;   et al.
2004-11-25
Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuit
App 20040153926 - Abdel-Hafez, Khader S. ;   et al.
2004-08-05
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
App 20030154433 - Wang, Laung-Terng ;   et al.
2003-08-14
Method and system to optimize test cost and disable defects for scan and BIST memories
App 20020194558 - Wang, Laung-Terng ;   et al.
2002-12-19
Multiple-capture DFT system for scan-based integrated circuits
App 20020184560 - Wang, Laung-Terng ;   et al.
2002-12-05
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
App 20020138801 - Wang, Laung-Terng ;   et al.
2002-09-26
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
App 20020120896 - Wang, Laung-Terng ;   et al.
2002-08-29

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