Wang; Jianshi
Patent Applications and Registrations
Patent applications and USPTO patent grants for Wang; Jianshi.The latest application filed is for "semiconductor device having triple ldd structure and lower gate resistance formed with a single implant process".
- Wang; Jianshi - San Jose CA
Trademarks
| Patent | Date |
|---|---|
| Semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process Grant 7,084,458 - Khan , et al. August 1, 2 | 2006-08-01 |
| Method for fabricating a flash memory device Grant 6,939,766 - He , et al. September 6, 2 | 2005-09-06 |
| Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process Grant 6,939,770 - Khan , et al. September 6, 2 | 2005-09-06 |
| System and method for charge restoration in a non-volatile memory device Grant 6,751,146 - Wang , et al. June 15, 2 | 2004-06-15 |
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