loadpatents
name:-0.039669990539551
name:-0.026411056518555
name:-0.0010771751403809
Wang; Hsin-Po Patent Filings

Wang; Hsin-Po

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wang; Hsin-Po.The latest application filed is for "method and apparatus for broadcasting scan patterns in a scan-based integrated circuit".

Company Profile
0.25.31
  • Wang; Hsin-Po - Hsinchu TW
  • Wang; Hsin-Po - Hsinchu City TW
  • Wang; Hsin Po - Tao Yuan TW
  • Wang; Hsin-Po - Hsin-Chu TW
  • Wang; Hsin-Po - Taoyuan County TW
  • Wang; Hsin-Po - Chu-Tung TW
  • Wang; Hsin Po - Tao Yuan City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Creating gateway model routing sub-templates
Grant 10,990,743 - Yuan , et al. April 27, 2
2021-04-27
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 9,696,377 - Wang , et al. July 4, 2
2017-07-04
Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit
App 20150338461 - Wang; Laung-Terng ;   et al.
2015-11-26
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 9,121,902 - Wang , et al. September 1, 2
2015-09-01
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 9,110,139 - Wang , et al. August 18, 2
2015-08-18
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 9,057,763 - Wang , et al. June 16, 2
2015-06-16
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 9,026,875 - Wang , et al. May 5, 2
2015-05-05
Gateway model routing with slits on wires
Grant 8,990,756 - Wang , et al. March 24, 2
2015-03-24
Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit
App 20140344636 - Wang; Laung-Terng ;   et al.
2014-11-20
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 8,769,359 - Wang , et al. July 1, 2
2014-07-01
Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit
App 20140149816 - Wang; Laung-Terng ;   et al.
2014-05-29
Gateway Model Routing with Slits on Wires
App 20140143747 - Wang; Hsin-Po ;   et al.
2014-05-22
Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test
App 20140082446 - Wang; Laung-Terng ;   et al.
2014-03-20
Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test
App 20140075256 - Wang; Laung-Terng ;   et al.
2014-03-13
Method Of Improving Cursor Operation Of Handheld Pointer Device In A Display And Handheld Pointer Device With Improved Cursor Operation
App 20130314318 - Tseng; Ching-Hung ;   et al.
2013-11-28
Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test
App 20130268818 - Wang; Laung-Terng ;   et al.
2013-10-10
Computer-aided design system to automate scan synthesis at register-transfer level
Grant 8,543,950 - Wang , et al. September 24, 2
2013-09-24
Computer-aided Design System To Automate Scan Synthesis At Register-transfer Level
App 20120246604 - WANG; Laung-Terng (L. -T.) ;   et al.
2012-09-27
Method Of Improving Operation Of Handheld Pointer Device In A Display Screen
App 20120212513 - Tseng; Ching-Hung ;   et al.
2012-08-23
Methods and systems for reducing clock skew in a gated clock tree
Grant 8,086,982 - Chang , et al. December 27, 2
2011-12-27
System for implementing post-silicon IC design changes
Grant 8,015,522 - Wang , et al. September 6, 2
2011-09-06
Multiple-capture DFT system for scan-based integrated circuits
Grant 7,904,773 - Wang , et al. March 8, 2
2011-03-08
Power control apparatus and method for an optical drive
Grant 7,808,871 - Wang , et al. October 5, 2
2010-10-05
Methods And Systems For Reducing Clock Skew In A Gated Clock Tree
App 20100225353 - CHANG; Chia-Ming ;   et al.
2010-09-09
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 7,779,323 - Wang , et al. August 17, 2
2010-08-17
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 7,721,173 - Wang , et al. May 18, 2
2010-05-18
Method And Apparatus For Broadcasting Scan Patterns In A Scan-based Integrated Circuit
App 20090235132 - Wang; Laung-Terng ;   et al.
2009-09-17
System For Implementing Post-silicon Ic Design Changes
App 20090178013 - Wang; Hsin-Po ;   et al.
2009-07-09
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
Grant 7,552,373 - Wang , et al. June 23, 2
2009-06-23
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
App 20090132880 - Wang; Laung-Terng (L.- T.) ;   et al.
2009-05-21
Multiple-Capture DFT system for scan-based integrated circuits
App 20090070646 - Wang; Laung-Terng (L.T.) ;   et al.
2009-03-12
Method and apparatus for unifying self-test with scan-test during prototype debug and production test
App 20090037786 - Wang; Laung-Terng ;   et al.
2009-02-05
IC functional and delay fault testing
Grant 7,461,310 - Wang December 2, 2
2008-12-02
Method for optimizing write parameters of optical storage medium and recording device therefor
Grant 7,450,482 - Lee , et al. November 11, 2
2008-11-11
Method and apparatus for unifying self-test with scan-test during prototype debug and production test
Grant 7,444,567 - Wang , et al. October 28, 2
2008-10-28
Method Of Testing High-speed Ic With Low-speed Ic Tester
App 20080082880 - Wang; Hsin-Po ;   et al.
2008-04-03
Computer-aided design system to automate scan synthesis at register-transfer level
Grant 7,331,032 - Wang , et al. February 12, 2
2008-02-12
IC functional and delay fault testing
App 20070288818 - Wang; Hsin-Po
2007-12-13
Power control apparatus and method for an optical drive
App 20070217299 - Wang; Hsin Po ;   et al.
2007-09-20
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
Grant 7,191,373 - Wang , et al. March 13, 2
2007-03-13
Method For Optimizing Write Parameters Of Optical Storage Medium And Recording Device Therefor
App 20070041293 - Lee; Yao-Yu ;   et al.
2007-02-22
Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
Grant 7,058,869 - Abdel-Hafez , et al. June 6, 2
2006-06-06
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
Grant 7,007,213 - Wang , et al. February 28, 2
2006-02-28
Multiple-capture DFT system for scan-based integrated circuits
App 20050235186 - Wang, Laung-Terng ;   et al.
2005-10-20
Multiple-capture DFT system for scan-based integrated circuits
Grant 6,954,887 - Wang , et al. October 11, 2
2005-10-11
Method and apparatus for unifying self-test with scan-test during prototype debug and production test
App 20040268181 - Wang, Laung-Terng ;   et al.
2004-12-30
Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
App 20040237015 - Abdel-Hafez, Khader S. ;   et al.
2004-11-25
Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuit
App 20040153926 - Abdel-Hafez, Khader S. ;   et al.
2004-08-05
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
App 20030154433 - Wang, Laung-Terng ;   et al.
2003-08-14
Computer-aided design system to automate scan synthesis at register-transfer level
App 20030023941 - Wang, Laung-Terng (L.-T.) ;   et al.
2003-01-30
Method and system to optimize test cost and disable defects for scan and BIST memories
App 20020194558 - Wang, Laung-Terng ;   et al.
2002-12-19
Multiple-capture DFT system for scan-based integrated circuits
App 20020184560 - Wang, Laung-Terng ;   et al.
2002-12-05
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
App 20020138801 - Wang, Laung-Terng ;   et al.
2002-09-26
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
App 20020120896 - Wang, Laung-Terng ;   et al.
2002-08-29

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed