| Patent | Date |
|---|
DRAM with inter-section, page-data-copy scheme for low power and wide data access
App 20220130450 - Wang; Gyh-Bin ; et al. | 2022-04-28 |
Method and apparatus for Data Processing in Conjunction with Memory Array Access
App 20220100816 - Wang; Gyh-Bin ; et al. | 2022-03-31 |
DRAM with inter-section, page-data-copy scheme for low power and wide data access
Grant 11,250,904 - Wang , et al. February 15, 2 | 2022-02-15 |
Apparatus for enhancing prefetch access in memory module
Grant 11,183,231 - Wang , et al. November 23, 2 | 2021-11-23 |
Apparatus For Enhancing Prefetch Access In Memory Module
App 20210158856 - Wang; Gyh-Bin ; et al. | 2021-05-27 |
Semiconductor chip set with double-sided off-chip bonding structure
Grant 10,978,377 - Wang April 13, 2 | 2021-04-13 |
Semiconductor Chip Set with Double-Sided Off-chip Bonding Structure
App 20200211930 - WANG; GYH-BIN | 2020-07-02 |
Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer
Grant 10,559,374 - Wang , et al. Feb | 2020-02-11 |
Circuit Topology Of Memory Chips With Embedded Function Test Pattern Generation Module Connected To Normal Access Port Physical Layer
App 20180240531 - Wang; Gyh-Bin ; et al. | 2018-08-23 |
Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank
Grant 9,997,224 - Wang , et al. June 12, 2 | 2018-06-12 |
Memory Architecture With Multi-bank Memory Cell Array Accessed By Local Drive Circuit Within Memory Bank
App 20180068700 - Wang; Ming-Hung ; et al. | 2018-03-08 |
Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system
Grant 9,679,622 - Wang , et al. June 13, 2 | 2017-06-13 |
Multi-bank memory device and system
Grant 9,653,148 - Ting , et al. May 16, 2 | 2017-05-16 |
Memory architecture dividing memory cell array into independent memory banks
Grant 9,466,355 - Ting , et al. October 11, 2 | 2016-10-11 |
Memory Architecture Dividing Memory Cell Array Into Independent Memory Banks
App 20150332751 - Ting; Tah-Kang Joseph ; et al. | 2015-11-19 |
Method For Controlling Memory Device Asynchronously With Respect To System Clock, And Related Memory Device And Memory System
App 20150287445 - Wang; Gyh-Bin ; et al. | 2015-10-08 |
High speed test circuit and method
Grant 8,754,656 - Ting , et al. June 17, 2 | 2014-06-17 |
High Speed Test Circuit and Method
App 20120229146 - Ting; Tah-Kang ; et al. | 2012-09-13 |
Digitized image stabilization using energy analysis method
Grant 7,961,966 - Wang , et al. June 14, 2 | 2011-06-14 |
Method and circuit for transferring data stream across multiple clock domains
Grant 7,860,202 - Wang , et al. December 28, 2 | 2010-12-28 |
Multiphase DLL using 3-edge phase detector for wide-range operation
App 20090009224 - Wang; Gyh-Bin ; et al. | 2009-01-08 |
Digitized image stabilization using energy analysis method
App 20060146139 - Wang; Gyh-Bin ; et al. | 2006-07-06 |
LCD controller which supports a no-scaling image without a frame buffer
Grant 6,943,783 - Ting , et al. September 13, 2 | 2005-09-13 |
Noise reduction method and system for a multiple clock, mixed signal integrated circuit
Grant 6,791,382 - Ting , et al. September 14, 2 | 2004-09-14 |
DDR DRAM data coherence scheme
Grant 6,453,381 - Yuan , et al. September 17, 2 | 2002-09-17 |
High efficiency CMOS pump circuit
Grant 6,198,340 - Ting , et al. March 6, 2 | 2001-03-06 |
Address decoding scheme for DDR memory
Grant 6,130,853 - Wang , et al. October 10, 2 | 2000-10-10 |
Multiple phase synchronous race delay clock distribution circuit with skew compensation
Grant 5,999,032 - Wang , et al. December 7, 1 | 1999-12-07 |
Latched type clock synchronizer with additional 180.degree.-phase shift clock
Grant 5,923,613 - Tien , et al. July 13, 1 | 1999-07-13 |
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