Walling; Paul R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Walling; Paul R..The latest application filed is for "semiconductor package metal shadowing checks".

Company Profile

6.16.13

Walling; Paul R. - Austin TX
Walling; Paul R. - White Plains NY US
Walling; Paul R. - Lagrangeville NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor package metal shadowing checks Grant 10,956,649 - Call , et al. March 23, 2	2021-03-23
Semiconductor package floating metal checks Grant 10,949,600 - Audet , et al. March 16, 2	2021-03-16
Semiconductor package via stack checking Grant 10,546,096 - Call , et al. Ja	2020-01-28
Semiconductor Package Metal Shadowing Checks App 20190377850 - Call; Anson J. ; et al.	2019-12-12
Semiconductor Package Floating Metal Checks App 20190362049 - Audet; Jean ; et al.	2019-11-28
Semiconductor package floating metal checks Grant 10,423,751 - Audet , et al. Sept	2019-09-24
Semiconductor package metal shadowing checks Grant 10,423,752 - Call , et al. Sept	2019-09-24
Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures Grant 10,375,820 - Choi , et al.	2019-08-06
Semiconductor Package Via Stack Checking App 20190102504 - Call; Anson J. ; et al.	2019-04-04
Semiconductor Package Metal Shadowing Checks App 20190102506 - Call; Anson J. ; et al.	2019-04-04
Semiconductor Package Floating Metal Checks App 20190102505 - Audet; Jean ; et al.	2019-04-04
Crosstalk Reduction Between Signal Layers In A Multilayered Package By Variable-width Mesh Plane Structures App 20180213636 - CHOI; JINWOO ; et al.	2018-07-26
Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures Grant 9,955,567 - Choi , et al. April 24, 2	2018-04-24
Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures Grant 8,927,879 - Choi , et al. January 6, 2	2015-01-06
Crosstalk Reduction Between Signal Layers In A Multilayered Package By Variable-width Mesh Plane Structures App 20140331482 - CHOI; JINWOO ; et al.	2014-11-13
Elastic modulus mapping of a chip carrier in a flip chip package Grant 8,756,546 - Cohen , et al. June 17, 2	2014-06-17
Elastic Modulus Mapping Of A Chip Carrier In A Flip Chip Package App 20140033148 - Cohen; Erwin B. ; et al.	2014-01-30
Crosstalk Reduction Between Signal Layers In A Multilayered Package By Variable-width Mesh Plane Structures App 20120125677 - Choi; Jinwoo ; et al.	2012-05-24
Nested design approach Grant 7,325,213 - Bhatia , et al. January 29, 2	2008-01-29
Mesh plane generation and file storage Grant 7,096,451 - Donaldson , et al. August 22, 2	2006-08-22
Nested Design Approach App 20050278674 - Bhatia, Harsaran S. ; et al.	2005-12-15
Mesh Plane Generation And File Storage App 20050055660 - Donaldson, Alice L. ; et al.	2005-03-10
Substrate Design Of A Chip Using A Generic Substrate Design App 20030047352 - Bhatia, Harsaran S. ; et al.	2003-03-13
Direct deposit thin film single/multi chip module Grant 6,261,467 - Giri , et al. July 17, 2	2001-07-17
Direct deposit thin film single/multi chip module Grant 6,037,044 - Giri , et al. March 14, 2	2000-03-14
Method and apparatus for designing a module Grant 5,677,847 - Walling October 14, 1	1997-10-14

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