loadpatents
name:-0.014490127563477
name:-0.0027749538421631
name:-0.0085151195526123
Wall; Marcel Patent Filings

Wall; Marcel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wall; Marcel.The latest application filed is for "dielectric-to-metal adhesion promotion material".

Company Profile
7.2.11
  • Wall; Marcel - Phoenix AZ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Dielectric-to-metal Adhesion Promotion Material
App 20220293509 - Manepalli; Rahul ;   et al.
2022-09-15
Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures
Grant 11,445,616 - Nad , et al. September 13, 2
2022-09-13
Selectively Roughened Copper Architectures For Low Insertion Loss Conductive Features
App 20220102259 - Kong; Jieying ;   et al.
2022-03-31
Electronic Substrates Having Embedded Inductors
App 20220093316 - Duong; Benjamin ;   et al.
2022-03-24
Electroless Plating Process
App 20220010452 - NAIR; Chandrasekharan ;   et al.
2022-01-13
Package architecture with improved via drill process and method for forming such package
Grant 11,177,234 - Nad , et al. November 16, 2
2021-11-16
Multiple Layer Copper Seeding
App 20210090946 - GRUJICIC; Darko ;   et al.
2021-03-25
Controlled Organic Layers To Enhance Adhesion To Organic Dielectrics And Process For Forming Such
App 20200312768 - NAD; Suddhasattwa ;   et al.
2020-10-01
Copper Interface Features For High Speed Interconnect Applications
App 20200315023 - NAD; Suddhasattwa ;   et al.
2020-10-01
Hybrid Fine Line Spacing Architecture For Bump Pitch Scaling
App 20200312665 - NAD; Suddhasattwa ;   et al.
2020-10-01
Selective Metal Deposition By Patterning Direct Electroless Metal Plating
App 20200251332 - Kind Code
2020-08-06
Package Architecture With Improved Via Drill Process And Method For Forming Such Package
App 20190393183 - NAD; Suddhasattwa ;   et al.
2019-12-26
Interfacial Layer For High Resolution Lithography (hrl) And High Speed Input/output (io Or I/o) Architectures
App 20190320537 - NAD; Suddhasattwa ;   et al.
2019-10-17

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