| Patent | Date |
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Technology migration for integrated circuits with radical design restrictions
Grant 8,464,189 - Allen , et al. June 11, 2 | 2013-06-11 |
Schematic-based Layout Migration
App 20120233576 - Barrows; Geoffrey R. ; et al. | 2012-09-13 |
Adaptive weighting method for layout optimization with multiple priorities
Grant 7,895,562 - Gray , et al. February 22, 2 | 2011-02-22 |
Integrated circuit selective scaling
Grant 7,882,463 - Heng , et al. February 1, 2 | 2011-02-01 |
Layout optimization using parameterized cells
Grant 7,865,848 - Gernhoefer , et al. January 4, 2 | 2011-01-04 |
IC layout optimization to improve yield
Grant 7,818,694 - Allen , et al. October 19, 2 | 2010-10-19 |
Technology Migration For Integrated Circuits With Radical Design Restrictions
App 20100185997 - Allen; Robert J. ; et al. | 2010-07-22 |
Technology migration for integrated circuits with radical design restrictions
Grant 7,761,821 - Allen , et al. July 20, 2 | 2010-07-20 |
Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design
Grant 7,752,589 - Allen , et al. July 6, 2 | 2010-07-06 |
Context aware sub-circuit layout modification
Grant 7,735,042 - Gray , et al. June 8, 2 | 2010-06-08 |
Technology migration for integrated circuits with radical design restrictions
Grant 7,610,565 - Allen , et al. October 27, 2 | 2009-10-27 |
Independent migration of hierarchical designs with methods of finding and fixing opens during migration
Grant 7,568,173 - Gernhoefer , et al. July 28, 2 | 2009-07-28 |
Adaptive Weighting Method For Layout Optimization With Multiple Priorities
App 20090158223 - Gray; Michael S. ; et al. | 2009-06-18 |
IC Layout Optimization to Improve Yield
App 20090100386 - Allen; Robert J. ; et al. | 2009-04-16 |
IC layout optimization to improve yield
Grant 7,503,020 - Allen , et al. March 10, 2 | 2009-03-10 |
Layout Optimization Using Parameterized Cells
App 20090064061 - Gernhoefer; Veit ; et al. | 2009-03-05 |
Context Aware Sub-circuit Layout Modification
App 20090037851 - Gray; Michael S. ; et al. | 2009-02-05 |
Polygonal Area Design Rule Correction Method For Vlsi Layouts
App 20090037850 - Gray; Michael S. ; et al. | 2009-02-05 |
Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs
Grant 7,484,197 - Allen , et al. January 27, 2 | 2009-01-27 |
Independent Migration Of Hierarchical Designs With Methods Of Finding And Fixing Opens During Migration
App 20080313581 - Gernhoefer; Veit ; et al. | 2008-12-18 |
Method, apparatus and computer program product for optimizing an integrated circuit layout
Grant 7,454,721 - Hibbeler , et al. November 18, 2 | 2008-11-18 |
Method Of Optimizing Hierarchical Very Large Scale Integration (vlsi) Design By Use Of Cluster-based Logic Cell Cloning
App 20080172638 - Gray; Michael S. ; et al. | 2008-07-17 |
Method, Apparatus, And Computer Program Product For Displaying And Modifying The Critical Area Of An Integrated Circuit Design.
App 20080168414 - Allen; Robert J. ; et al. | 2008-07-10 |
Integrated Circuit Selective Scaling
App 20080148210 - Heng; Fook-Luen ; et al. | 2008-06-19 |
Integrated circuit selective scaling
Grant 7,363,601 - Heng , et al. April 22, 2 | 2008-04-22 |
IC Layout Optimization To Improve Yield
App 20070294648 - Allen; Robert J. ; et al. | 2007-12-20 |
Technology Migration For Integrated Circuits With Radical Design Restrictions
App 20070277129 - Allen; Robert J. ; et al. | 2007-11-29 |
Technology migration for integrated circuits with radical design restrictions
Grant 7,302,651 - Allen , et al. November 27, 2 | 2007-11-27 |
Minimum Layout Perturbation-based Artwork Legalization With Grid Constraints For Hierarchical Designs
App 20070245283 - Allen; RobertJ ; et al. | 2007-10-18 |
Technology Migration For Integrated Circuits With Radical Design Restrictions
App 20070198961 - Allen; Robert J. ; et al. | 2007-08-23 |
Integrated circuit yield enhancement using Voronoi diagrams
Grant 7,260,790 - Allen , et al. August 21, 2 | 2007-08-21 |
Technology migration for integrated circuits with radical design restrictions
Grant 7,257,783 - Allen , et al. August 14, 2 | 2007-08-14 |
Cloned and original circuit shape merging
Grant 7,120,887 - Bonges, III , et al. October 10, 2 | 2006-10-10 |
Circuit area minimization using scaling
Grant 7,117,456 - Gray , et al. October 3, 2 | 2006-10-03 |
Integrated Circuit Yield Enhancement Using Voronoi Diagrams
App 20060150130 - Allen; Robert J. ; et al. | 2006-07-06 |
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization
Grant 7,062,729 - Gray , et al. June 13, 2 | 2006-06-13 |
Technology Migration For Integrated Circuits With Radical Design Restrictions
App 20060101356 - Allen; Robert J. ; et al. | 2006-05-11 |
Technology Migration For Integrated Circuits With Radical Design Restrictions
App 20060101357 - Allen; Robert J. ; et al. | 2006-05-11 |
Integrated Circuit Selective Scaling
App 20060085768 - Heng; Fook-Luen ; et al. | 2006-04-20 |
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization
App 20060064661 - Gray; Michael S. ; et al. | 2006-03-23 |
Cloned And Original Circuit Shape Merging
App 20050160390 - Bonges, Henry A. III ; et al. | 2005-07-21 |
Circuit Area Minimization Using Scaling
App 20050125748 - Gray, Michael S. ; et al. | 2005-06-09 |
Entity control for raster displays
Grant 4,516,266 - Christopher , et al. May 7, 1 | 1985-05-07 |
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