Wahl; Jeremy A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wahl; Jeremy A..The latest application filed is for "interconnect structures with airgaps and dielectric-capped interconnects".

Company Profile

2.17.15

Wahl; Jeremy A. - Portland OR
Wahl; Jeremy A. - Delmar NY
Wahl; Jeremy A. - Malta NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Interconnect Structures With Airgaps And Dielectric-capped Interconnects App 20200227308 - LiCausi; Nicholas V. ; et al.	2020-07-16
Interconnect structures with airgaps and dielectric-capped interconnects Grant 10,707,119 - LiCausi , et al.	2020-07-07
Method of manufacturing selective nanostructures into finFET process flow Grant 10,049,944 - Beasor , et al. August 14, 2	2018-08-14
Method Of Manufacturing Selective Nanostructures Into Finfet Process Flow App 20180096899 - BEASOR; Scott ; et al.	2018-04-05
Integrated circuits with dual silicide contacts and methods for fabricating same Grant 9,660,075 - Koh , et al. May 23, 2	2017-05-23
Methods of forming FinFET devices with substantially undoped channel regions Grant 9,634,143 - Wahl , et al. April 25, 2	2017-04-25
Integrated Circuits With Dual Silicide Contacts And Methods For Fabricating Same App 20160172493 - Koh; Shao Ming ; et al.	2016-06-16
Integrated circuits with dual silicide contacts and methods for fabricating same Grant 9,293,462 - Koh , et al. March 22, 2	2016-03-22
Integrated Circuits With Dual Silicide Contacts And Methods For Fabricating Same App 20160049490 - Bouche; Guillaume ; et al.	2016-02-18
Integrated circuits with dual silicide contacts and methods for fabricating same Grant 9,196,694 - Bouche , et al. November 24, 2	2015-11-24
Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same Grant 9,177,805 - Bouche , et al. November 3, 2	2015-11-03
Integrated Circuits With Metal-insulator-semiconductor (mis) Contact Structures And Methods For Fabricating Same App 20150214059 - Bouche; Guillaume ; et al.	2015-07-30
Iintegrated Circuits With Dual Silicide Contacts And Methods For Fabricating Same App 20150214228 - Koh; Shao Ming ; et al.	2015-07-30
Integrated Circuits With Dual Silicide Contacts And Methods For Fabricating Same App 20150091093 - Bouche; Guillaume ; et al.	2015-04-02
Methods of forming a masking layer for patterning underlying structures Grant 8,969,207 - Schmid , et al. March 3, 2	2015-03-03
Strained silicon carbide channel for electron mobility of NMOS Grant 8,963,255 - Wahl , et al. February 24, 2	2015-02-24
Methods of forming trench/via features in an underlying structure using a process that includes a masking layer formed by a directed self-assembly process Grant 8,906,802 - Wahl , et al. December 9, 2	2014-12-09
Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process Grant 8,853,019 - Fronheiser , et al. October 7, 2	2014-10-07
Methods of trimming nanowire structures Grant 8,846,511 - LiCausi , et al. September 30, 2	2014-09-30
Methods Of Forming A Semiconductor Device With A Nanowire Channel Structure By Performing An Anneal Process App 20140273423 - Fronheiser; Jody A. ; et al.	2014-09-18
Methods Of Forming A Masking Layer For Patterning Underlying Structures App 20140273473 - Schmid; Gerard M. ; et al.	2014-09-18
Methods Of Forming Trench/via Features In An Underlying Structure Using A Process That Includes A Masking Layer Formed By A Directed Self-assembly Process App 20140273469 - Wahl; Jeremy A. ; et al.	2014-09-18
Methods Of Trimming Nanowire Structures App 20140227849 - LiCausi; Nicholas V. ; et al.	2014-08-14
Strained Silicon Carbide Channel For Electron Mobility Of Nmos App 20140203298 - WAHL; Jeremy A. ; et al.	2014-07-24
Electronic device having plural FIN-FETs with different FIN heights and planar FETs on the same substrate Grant 8,759,904 - Wahl , et al. June 24, 2	2014-06-24
Strained silicon carbide channel for electron mobility of NMOS Grant 8,722,482 - Wahl , et al. May 13, 2	2014-05-13
Methods of forming dielectrically isolated fins for a FinFET semiconductor by performing an etching process wherein the etch rate is modified via inclusion of a dopant material Grant 8,691,640 - LiCausi , et al. April 8, 2	2014-04-08
Combined Planar Fet And Fin-fet Devices And Methods App 20130049136 - Wahl; Jeremy A. ; et al.	2013-02-28
Strained Silicon Carbide Channel For Electron Mobility Of Nmos App 20110227094 - Wahl; Jeremy A. ; et al.	2011-09-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.