loadpatents
name:-0.0085139274597168
name:-0.008436918258667
name:-0.000640869140625
Wagner; Tina Patent Filings

Wagner; Tina

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wagner; Tina.The latest application filed is for "via selection in integrated circuit design".

Company Profile
0.8.6
  • Wagner; Tina - Newburgh NY
  • Wagner; Tina - Hopewell Junction NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Via selection in integrated circuit design
Grant 8,631,375 - Arelt , et al. January 14, 2
2014-01-14
Via Selection In Integrated Circuit Design
App 20130268908 - Arelt; Robert R. ;   et al.
2013-10-10
Automated sensitivity definition and calibration for design for manufacturing tools
Grant 8,141,027 - Culp , et al. March 20, 2
2012-03-20
Automated Sensitivity Definition And Calibration For Design For Manufacturing Tools
App 20110166686 - Culp; James A. ;   et al.
2011-07-07
Intersect area based ground rule for semiconductor design
Grant 7,941,780 - Avanessian , et al. May 10, 2
2011-05-10
Intersect Area Based Ground Rule For Semiconductor Design
App 20090265673 - Avanessian; Albrik ;   et al.
2009-10-22
Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
Grant 7,337,420 - Chidambarrao , et al. February 26, 2
2008-02-26
Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
App 20070028195 - Chidambarrao; Dureseti ;   et al.
2007-02-01
Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials
Grant 6,869,542 - Desphande , et al. March 22, 2
2005-03-22
Hard Mask Integrated Etch Process For Patterning Of Silicon Oxide And Other Dielectric Materials
App 20040178169 - Desphande, Sadanand V. ;   et al.
2004-09-16
Structure and method for formation of a blocked silicide resistor
Grant 6,660,664 - Adkisson , et al. December 9, 2
2003-12-09
Hard mask process to prevent surface roughness for selective dielectric etching
Grant 6,345,399 - Jamison , et al. February 12, 2
2002-02-12

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