WAFER-LEVEL PACKAGING PORTFOLIO LLC

Patent Applications and Registrations

Patent applications and USPTO patent grants for WAFER-LEVEL PACKAGING PORTFOLIO LLC.The latest application filed is for "process for making contact with and housing integrated circuits".

Company Profile

2.8.5

WAFER-LEVEL PACKAGING PORTFOLIO LLC - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Process for Making Contact with and Housing Integrated Circuits App 20130137259 - Bieck; Florian ; et al.	2013-05-30
Method for packing semiconductor components and product produced according to the method Grant 8,420,445 - Leib April 16, 2	2013-04-16
Method for packaging electronic devices and integrated circuits Grant 8,399,293 - Leib , et al. March 19, 2	2013-03-19
Process for making contact with and housing integrated circuits Grant 8,349,707 - Bieck , et al. January 8, 2	2013-01-08
Process for packaging components, and packaged components Grant 8,309,384 - Leib November 13, 2	2012-11-13
Method for producing electronic components Grant 8,114,304 - Leib , et al. February 14, 2	2012-02-14
Method for Packaging Electronic Devices and Integrated Circuits App 20120003791 - Leib; Juergen ; et al.	2012-01-05
Method for packaging electronic devices and integrated circuits Grant 8,017,435 - Leib , et al. September 13, 2	2011-09-13
Dual Interconnection in Stacked Memory and Controller Module App 20110169171 - Marcoux; Phil P.	2011-07-14
Process for making contact with and housing integrated circuits Grant 7,880,179 - Bieck , et al. February 1, 2	2011-02-01
Semiconductor with Bottom-Side Wrap-Around Flange Contact App 20100327448 - Marcoux; Phil P.	2010-12-30
Semiconductor with bottom-side wrap-around flange contact Grant 7,858,512 - Marcoux December 28, 2	2010-12-28
Dual Interconnection in Stacked Memory and Controller Module App 20100270668 - Marcoux; Phil P.	2010-10-28

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