| Patent | Date |
|---|
Jet Engine
App 20210293182 - NAKO; Shotaro ; et al. | 2021-09-23 |
Method of manufacturing sealed electronic component and sealed electronic component
Grant 7,902,481 - Kigawa , et al. March 8, 2 | 2011-03-08 |
Method Of Manufacturing Sealed Electronic Component And Sealed Electronic Component
App 20070199925 - Kigawa; Keisuke ; et al. | 2007-08-30 |
Semiconductor memory device having read data multiplexer
Grant 6,519,187 - Wada February 11, 2 | 2003-02-11 |
Semiconductor memory device having read data multiplexer
App 20020012276 - Wada, Tomohisa | 2002-01-31 |
Semiconductor Memory Device And Computer Having A Synchronization Signal Indicating That The Memory Data Output Is Valid
App 20010047449 - WADA, TOMOHISA | 2001-11-29 |
Synchronous semiconductor memory device having set up time of external address signal reduced
Grant 6,026,036 - Sekiya , et al. February 15, 2 | 2000-02-15 |
High voltage generation circuit which generates high voltage by digitally adjusting current amount flowing through capacitor
Grant 6,023,190 - Wada February 8, 2 | 2000-02-08 |
Semiconductor integrated circuit device with adjustable high voltage detection circuit
Grant 6,008,674 - Wada , et al. December 28, 1 | 1999-12-28 |
Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells
Grant 5,966,324 - Wada , et al. October 12, 1 | 1999-10-12 |
Computer graphics apparatus utilizing cache memory
Grant 5,959,639 - Wada September 28, 1 | 1999-09-28 |
Semiconductor memory device adaptable to external power supplies of different voltage levels
Grant 5,929,539 - Kozaru , et al. July 27, 1 | 1999-07-27 |
Bipolar transistor formed by a high energy ion implantation method
Grant 5,856,218 - Kinoshita , et al. January 5, 1 | 1999-01-05 |
Static type semiconductor memory with latch circuit amplifying read data read on a sub bit line pair and transferring the amplified read data to a main bit line pair and operation method thereof
Grant 5,850,367 - Wada , et al. December 15, 1 | 1998-12-15 |
Semiconductor memory device including a tag memory
Grant 5,841,961 - Kozaru , et al. November 24, 1 | 1998-11-24 |
Semiconductor memory device having improved wiring architecture
Grant 5,808,930 - Wada , et al. September 15, 1 | 1998-09-15 |
Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same
Grant 5,781,468 - Matsuo , et al. July 14, 1 | 1998-07-14 |
Method of executing read and write operations in a synchronous random access memory
Grant 5,752,270 - Wada May 12, 1 | 1998-05-12 |
Static Semiconductor memory device
Grant 5,724,292 - Wada March 3, 1 | 1998-03-03 |
Semiconductor memory device having two layers of bit lines arranged crossing with each other
Grant 5,699,308 - Wada , et al. December 16, 1 | 1997-12-16 |
Static type semiconductor memory device capable of operating at a low voltage and reducing a memory cell area
Grant 5,687,111 - Wada , et al. November 11, 1 | 1997-11-11 |
Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same
Grant 5,663,905 - Matsuo , et al. September 2, 1 | 1997-09-02 |
Semiconductor memory device capable of refresh operation in burst mode
Grant 5,659,515 - Matsuo , et al. August 19, 1 | 1997-08-19 |
Semiconductor memory device having two layers of bit lines arranged crossing with each other
Grant 5,563,820 - Wada , et al. October 8, 1 | 1996-10-08 |
Circuit for repairing defective bit in semiconductor memory device and repairing method
Grant 5,471,427 - Murakami , et al. * November 28, 1 | 1995-11-28 |
Circuit for repairing defective bit in semiconductor memory device and repairing method
Grant 5,379,258 - Murakami , et al. * January 3, 1 | 1995-01-03 |
Semiconductor memory device having improved bit line arrangement
Grant 5,307,307 - Wada , et al. April 26, 1 | 1994-04-26 |
Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits
Grant 5,301,155 - Wada , et al. April 5, 1 | 1994-04-05 |
Semiconductor memory device
Grant 5,280,441 - Wada , et al. January 18, 1 | 1994-01-18 |
Circuit for repairing defective bit in semiconductor memory device and repairing method
Grant 5,134,585 - Murakami , et al. July 28, 1 | 1992-07-28 |
Static semiconductor memory device with predetermined threshold voltages
Grant 5,020,029 - Ichinose , et al. May 28, 1 | 1991-05-28 |
CMOS output circuit with intermediate potential setting means
Grant 4,988,888 - Hirose , et al. January 29, 1 | 1991-01-29 |
Semiconductor memory device with changeable word organization modes including a test mode
Grant 4,907,203 - Wada , et al. March 6, 1 | 1990-03-06 |
Protection circuit for a semiconductor integrated circuit having bipolar transistors
Grant 4,811,155 - Kuriyama , et al. March 7, 1 | 1989-03-07 |
Static semiconductor memory device comprising word lines each operating at three different voltage levels
Grant 4,751,683 - Wada , et al. June 14, 1 | 1988-06-14 |
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