loadpatents
name:-0.046597957611084
name:-0.031559944152832
name:-0.00049901008605957
Vyvoda; Michael A. Patent Filings

Vyvoda; Michael A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vyvoda; Michael A..The latest application filed is for "system and methods for virtual cooking with recipe optimization".

Company Profile
0.27.39
  • Vyvoda; Michael A. - Redwood City CA
  • Vyvoda; Michael A. - Fremont CA
  • Vyvoda; Michael A. - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
System And Methods For Virtual Cooking With Recipe Matching
App 20130149676 - Tokuda; Yukie J. ;   et al.
2013-06-13
System And Methods For Virtual Cooking With Food Pairing
App 20130149677 - Slone; Josiah A. ;   et al.
2013-06-13
System And Methods For Virtual Cooking With Multi-course Planning
App 20130149678 - Tokuda; Yukie J. ;   et al.
2013-06-13
System And Methods For Virtual Cooking With Recipe Optimization
App 20130149679 - Tokuda; Yukie J. ;   et al.
2013-06-13
System And Methods For Virtual Cooking
App 20130149675 - Slone; Josiah A. ;   et al.
2013-06-13
Process for fabricating a dielectric film using plasma oxidation
Grant 7,816,188 - Vyvoda , et al. October 19, 2
2010-10-19
Rail Schottky device and method of making
Grant 7,511,352 - Vyvoda March 31, 2
2009-03-31
Electrically isolated pillars in active devices
Grant 7,413,945 - Vyvoda , et al. August 19, 2
2008-08-19
Electrically isolated pillars in active devices
Grant 7,245,000 - Vyvoda , et al. July 17, 2
2007-07-17
Low resistivity titanium silicide on heavily doped semiconductor
Grant 7,148,570 - Herner , et al. December 12, 2
2006-12-12
Low resistivity titanium silicide on heavily doped semiconductor
Grant 7,144,807 - Herner , et al. December 5, 2
2006-12-05
Patterning three dimensional structures
Grant 7,071,565 - Li , et al. July 4, 2
2006-07-04
Metal structures for integrated circuits and methods for making the same
Grant 7,018,878 - Vyvoda , et al. March 28, 2
2006-03-28
Integrated circuit feature layout for improved chemical mechanical polishing
Grant 6,982,476 - Cleeves , et al. January 3, 2
2006-01-03
Electrically isolated pillars in active devices
Grant 6,952,043 - Vyvoda , et al. October 4, 2
2005-10-04
Contacts for an improved high-density nonvolatile memory
App 20050012220 - Vyvoda, Michael A. ;   et al.
2005-01-20
Multiple-mode memory and method for forming same
Grant 6,839,262 - Vyvoda , et al. January 4, 2
2005-01-04
Inverted staggered thin film transistor with etch stop layer and method of making same
Grant 6,825,533 - Vyvoda November 30, 2
2004-11-30
Rail schottky device and method of making
App 20040232509 - Vyvoda, Michael A.
2004-11-25
Inverted staggered thin film transistor with salicided source/drain structures and method of making same
Grant 6,815,781 - Vyvoda , et al. November 9, 2
2004-11-09
Multiple-mode memory and method for forming same
App 20040184296 - Vyvoda, Michael A. ;   et al.
2004-09-23
Integrated circuit feature layout for improved chemical mechanical polishing
App 20040173904 - Cleeves, James M. ;   et al.
2004-09-09
Thermal processing for three dimensional circuits
Grant 6,770,939 - Subramanian , et al. August 3, 2
2004-08-03
Inverted staggered thin film transistor with etch stop layer and method of making same
App 20040145005 - Vyvoda, Michael A.
2004-07-29
Multiple-mode memory and method for forming same
Grant 6,768,661 - Vyvoda , et al. July 27, 2
2004-07-27
Formation of antifuse structure in a three dimensional memory
Grant 6,768,185 - Cleeves , et al. July 27, 2
2004-07-27
Electrically isolated pillars in active devices
App 20040087072 - Vyvoda, Michael A. ;   et al.
2004-05-06
Integrated circuit feature layout for improved chemical mechanical polishing
Grant 6,730,931 - Cleeves , et al. May 4, 2
2004-05-04
Electrically isolated pillars in active devices
App 20040071034 - Vyvoda, Michael A. ;   et al.
2004-04-15
Inverted staggered thin film transistor with etch stop layer and method of making same
Grant 6,710,409 - Vyvoda March 23, 2
2004-03-23
Anti-fuse memory cell with asymmetric breakdown voltage
Grant 6,704,235 - Knall , et al. March 9, 2
2004-03-09
Inverted staggered thin film transistor with salicided source/drain structures and method of making same
App 20040036124 - Vyvoda, Michael A. ;   et al.
2004-02-26
Method for fabricating and identifying integrated circuits and self-identifying integrated circuits
App 20040029357 - Vyvoda, Michael A. ;   et al.
2004-02-12
Multiple-mode memory and method for forming same
App 20040001348 - Vyvoda, Michael A. ;   et al.
2004-01-01
Electrically Isolated Pillars In Active Devices
App 20040002186 - Vyvoda, Michael A. ;   et al.
2004-01-01
Structure and method for wafer comprising dielectric and semiconductor
Grant 6,649,451 - Vyvoda , et al. November 18, 2
2003-11-18
Method for fabricating and identifying integrated circuits and self-identifying integrated circuits
Grant 6,649,505 - Vyvoda , et al. November 18, 2
2003-11-18
Patterning three dimensional structures
Grant 6,627,530 - Li , et al. September 30, 2
2003-09-30
Thermal processing for three dimensional circuits
Grant 6,624,011 - Subramanian , et al. September 23, 2
2003-09-23
Method For Fabricating And Identifying Integrated Circuits And Self-identifying Integrated Circuits
App 20030147266 - Vyvoda, Michael A. ;   et al.
2003-08-07
Method for storing digital information in write-once memory array
Grant 6,584,541 - Friedman , et al. June 24, 2
2003-06-24
Wafer surface that facilitates particle removal
App 20030102528 - Vyvoda, Michael A. ;   et al.
2003-06-05
Metal structures for integrated circuits and methods for making the same
App 20030087484 - Vyvoda, Michael A. ;   et al.
2003-05-08
Formation of antifuse structure in a three dimensional memory
Grant 6,541,312 - Cleeves , et al. April 1, 2
2003-04-01
Low resistivity titanium silicide on heavily doped semiconductor
App 20030030148 - Herner, Scott Brad ;   et al.
2003-02-13
Low resistivity titanium silicide on heavily doped semiconductor
App 20030030147 - Herner, Scott Brad ;   et al.
2003-02-13
Patterning three dimensional structures
App 20030025210 - Li, Calvin K. ;   et al.
2003-02-06
Anti-fuse memory cell with asymmetric breakdown voltage
App 20030026157 - Knall, N. Johan ;   et al.
2003-02-06
Thermal processing for three dimensional circuits
App 20030025176 - Subramanian, Vivek ;   et al.
2003-02-06
Anti-fuse memory cell with asymmetric breakdown voltage
App 20030026158 - Knall, N. Johan ;   et al.
2003-02-06
Process for fabricating a dielectric film using plasma oxidation
App 20030022526 - Vyvoda, Michael A. ;   et al.
2003-01-30
Formation of antifuse structure in a three dimensional memory
App 20030003632 - Cleeves, James M. ;   et al.
2003-01-02
Method of generating integrated circuit feature layout for improved chemical mechanical polishing
Grant 6,486,066 - Cleeves , et al. November 26, 2
2002-11-26
Method of forming nonvolatile memory device utilizing a hard mask
Grant 6,486,065 - Vyvoda , et al. November 26, 2
2002-11-26
Integrated circuit feature layout for improved chemical Mechanical polishing
App 20020104991 - Cleeves, James M. ;   et al.
2002-08-08
Wafer surface that facilitates particle removal
App 20020105057 - Vyvoda, Michael A. ;   et al.
2002-08-08
Method Of Generating Integrated Circuit Feature Layout For Improved Chemical Mechanical Polishing
App 20020106837 - Cleeves, James M. ;   et al.
2002-08-08
Formation of antifuse structure in a three dimensional memory
App 20020106838 - Cleeves, James M. ;   et al.
2002-08-08
Patterning three dimensional structures
App 20020081833 - Li, Calvin K. ;   et al.
2002-06-27
Method Of Forming Nonvolatile Memory Device Utilizing A Hard Mask
App 20020081851 - Vyvoda, Michael A. ;   et al.
2002-06-27
Method for storing digital information in write-once memory array
App 20020065983 - Friedman, David R. ;   et al.
2002-05-30

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed