| Patent | Date |
|---|
Threshold Logic Gates Using Flash Transistors
App 20220263508 - Vrudhula; Sarma ; et al. | 2022-08-18 |
FPGA with reconfigurable threshold logic gates for improved performance, power, and area
Grant 11,356,100 - Vrudhula , et al. June 7, 2 | 2022-06-07 |
Configurable Bnn Asic Using A Network Of Programmable Threshold Logic Standard Cells
App 20220121915 - Wagle; Ankit ; et al. | 2022-04-21 |
Fpga With Reconfigurable Threshold Logic Gates For Improved Performance, Power, And Area
App 20210013886 - Vrudhula; Sarma ; et al. | 2021-01-14 |
Non-volatile logic device for energy-efficient logic state restoration
Grant 10,795,809 - Yang , et al. October 6, 2 | 2020-10-06 |
Neural Network Circuitry
App 20200160159 - Azari; Elham ; et al. | 2020-05-21 |
Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs
Grant 10,551,869 - Vrudhula , et al. Fe | 2020-02-04 |
Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuits
Grant 10,447,249 - Vrudhula , et al. Oc | 2019-10-15 |
Non-volatile Logic Device For Energy-efficient Logic State Restoration
App 20190213119 - Yang; Jinghua ; et al. | 2019-07-11 |
Electrocardiographic Biometric Authentication
App 20190150794 - Vrudhula; Sarma ; et al. | 2019-05-23 |
Energy efficient, robust differential mode d-flip-flop
Grant 10,250,236 - Vrudhula , et al. | 2019-04-02 |
Processor control system
Grant 10,133,323 - Hanumaiah , et al. November 20, 2 | 2018-11-20 |
Energy Efficient, Robust Differential Mode D-flip-flop
App 20180159512 - Vrudhula; Sarma ; et al. | 2018-06-07 |
Hold Violation Free Scan Chain And Scanning Mechanism For Testing Of Synchronous Digital Vlsi Circuits
App 20180102766 - Vrudhula; Sarma ; et al. | 2018-04-12 |
Determining parameters that affect processor energy efficiency
Grant 9,933,825 - Hanumaiah , et al. April 3, 2 | 2018-04-03 |
Neuromorphic computational system(s) using resistive synaptic devices
Grant 9,934,463 - Seo , et al. April 3, 2 | 2018-04-03 |
Method of obfuscating digital logic circuits using threshold voltage
Grant 9,876,503 - Vrudhula , et al. January 23, 2 | 2018-01-23 |
Clock Skewing Strategy To Reduce Dynamic Power And Eliminate Hold-time Violations In Synchronous Digital Vlsi Designs
App 20170248989 - Vrudhula; Sarma ; et al. | 2017-08-31 |
Method Of Obfuscating Digital Logic Circuits Using Threshold Voltage
App 20170187382 - Vrudhula; Sarma ; et al. | 2017-06-29 |
Neuromorphic Computational System(s) Using Resistive Synaptic Devices
App 20160336064 - Seo; Jae-sun ; et al. | 2016-11-17 |
Robust, low power, reconfigurable threshold logic array
Grant 9,490,815 - Vrudhula , et al. November 8, 2 | 2016-11-08 |
Threshold logic element with stabilizing feedback
Grant 9,473,139 - Vrudhula , et al. October 18, 2 | 2016-10-18 |
Resistive cross-point architecture for robust data representation with arbitrary precision
Grant 9,466,362 - Yu , et al. October 11, 2 | 2016-10-11 |
Robust, Low Power, Reconfigurable Threshold Logic Array
App 20160164526 - Vrudhula; Sarma ; et al. | 2016-06-09 |
Threshold logic gates with resistive networks
Grant 9,356,598 - Vrudhula , et al. May 31, 2 | 2016-05-31 |
Threshold gate and threshold logic array
Grant 9,306,151 - Vrudhula , et al. April 5, 2 | 2016-04-05 |
Resistive Cross-point Architecture For Robust Data Representation With Arbitrary Precision
App 20160049195 - Yu; Shimeng ; et al. | 2016-02-18 |
Threshold Logic Gates With Resistive Networks
App 20160006437 - Vrudhula; Sarma ; et al. | 2016-01-07 |
Threshold Logic Element With Stabilizing Feedback
App 20160006438 - Vrudhula; Sarma ; et al. | 2016-01-07 |
Determining Parameters That Affect Processor Energy Efficiency
App 20140281609 - Hanumaiah; Vinay ; et al. | 2014-09-18 |
Processor Control System
App 20140277815 - Hanumaiah; Vinay ; et al. | 2014-09-18 |
Technology mapping for threshold and logic gate hybrid circuits
Grant 8,832,614 - Vrudhula , et al. September 9, 2 | 2014-09-09 |
Technology Mapping For Threshold And Logic Gate Hybrid Circuits
App 20130339914 - Vrudhula; Sarma ; et al. | 2013-12-19 |
Decomposition based approach for the synthesis of threshold logic circuits
Grant 8,601,417 - Gowda , et al. December 3, 2 | 2013-12-03 |
Threshold Gate And Threshold Logic Array
App 20130313623 - Vrudhula; Sarma ; et al. | 2013-11-28 |
Combinational equivalence checking for threshold logic circuits
Grant 8,181,133 - Gowda , et al. May 15, 2 | 2012-05-15 |
Threshold logic element having low leakage power and high performance
Grant 8,164,359 - Leshner , et al. April 24, 2 | 2012-04-24 |
Decomposition Based Approach For The Synthesis Of Threshold Logic Circuits
App 20110214095 - Gowda; Tejaswi ; et al. | 2011-09-01 |
Threshold Logic Element Having Low Leakage Power And High Performance
App 20100321061 - Leshner; Samuel ; et al. | 2010-12-23 |
Method of evaluating integrated circuit system performance using orthogonal polynomials
Grant 7,630,852 - Ghanta , et al. December 8, 2 | 2009-12-08 |
Combinational Equivalence Checking for Threshold Logic Circuits
App 20090235216 - Gowda; Tejaswi ; et al. | 2009-09-17 |
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