Voss; Peter H.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Voss; Peter H..The latest application filed is for "low-power cache system and method".
- Voss; Peter H. - Aromas CA
- Voss; Peter H. - Watsonville CA
- Voss; Peter H. - La Selva CA
- Voss; Peter H. - Eindhoven NL
| Patent | Date |
|---|---|
| Low-power cache system and method Grant 7,487,369 - Gupta , et al. February 3, 2 | 2009-02-03 |
| Method and apparatus to prevent latch-up in CMOS devices Grant 6,359,316 - Voss , et al. March 19, 2 | 2002-03-19 |
| Digital programmable delay element Grant 6,255,879 - Voss July 3, 2 | 2001-07-03 |
| Cache memory cell with a pre-programmed state Grant 6,070,229 - Voss May 30, 2 | 2000-05-30 |
| SRAM with ROM functionality Grant 5,923,582 - Voss July 13, 1 | 1999-07-13 |
| Dummy cell for providing a reference voltage in a memory array Grant 5,689,471 - Voss , et al. November 18, 1 | 1997-11-18 |
| Five transistor memory cell with shared power line Grant 5,453,950 - Voss , et al. September 26, 1 | 1995-09-26 |
| Random access memory with page addressing mode Grant 5,245,585 - Voss , et al. September 14, 1 | 1993-09-14 |
| Integrated output buffer logic circuit with a memory circuit Grant 5,087,840 - Davies , et al. February 11, 1 | 1992-02-11 |
| Fast static random access memory with high storage capacity Grant 5,040,152 - Voss , et al. August 13, 1 | 1991-08-13 |
| Matrix memory with redundancy and minimizes delay Grant 5,033,024 - O'Connell , et al. July 16, 1 | 1991-07-16 |
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