Voogel; Martin L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Voogel; Martin L..The latest application filed is for "power delivery network for active-on-active stacked integrated circuits".

Company Profile

2.44.1

Voogel; Martin L. - Niwot CO
Voogel; Martin L. - Los Altos CA
Voogel; Martin L. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
On-die virtual probes (ODVP) for integrated circuitries Grant 11,428,733 - Chen , et al. August 30, 2	2022-08-30
Power delivery network for active-on-active stacked integrated circuits Grant 11,270,977 - Jain , et al. March 8, 2	2022-03-08
Method and apparatus of package enabled ESD protection Grant 11,043,484 - Shi , et al. June 22, 2	2021-06-22
Power Delivery Network For Active-on-active Stacked Integrated Circuits App 20210143127 - JAIN; Praful ; et al.	2021-05-13
Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture Grant 10,963,411 - Voogel , et al. March 30, 2	2021-03-30
Regularity of fabrics in programmable logic devices Grant 10,726,181 - Voogel , et al.	2020-07-28
Rotated integrated circuit die and chip packages having the same Grant 9,882,562 - Voogel , et al. January 30, 2	2018-01-30
Structures and methods of preventing an unintentional state change in a data storage node of a latch Grant 7,907,461 - Nguyen , et al. March 15, 2	2011-03-15
Method and apparatus for trimming die-to-die variation of an on-chip generated voltage reference Grant 7,859,918 - Nguyen , et al. December 28, 2	2010-12-28
Charge pump and voltage regulator for body bias voltage Grant 7,504,877 - Voogel , et al. March 17, 2	2009-03-17
Single event upset in SRAM cells in FPGAs with high resistivity gate structures Grant 7,452,765 - Voogel , et al. November 18, 2	2008-11-18
Voltage regulator with variable drive strength for improved phase margin in integrated circuits Grant 7,400,123 - Voogel July 15, 2	2008-07-15
Circuits and methods of implementing flip-flops in dual-output lookup tables Grant 7,385,416 - Chirania , et al. June 10, 2	2008-06-10
Lookup table circuits programmable to implement flip-flops Grant 7,378,869 - Chirania , et al. May 27, 2	2008-05-27
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Grant 7,376,000 - Voogel , et al. May 20, 2	2008-05-20
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Grant 7,301,796 - Voogel , et al. November 27, 2	2007-11-27
Data monitoring for single event upset in a programmable logic device Grant 7,283,409 - Voogel , et al. October 16, 2	2007-10-16
Programmable memory element with power save mode in a programmable logic device Grant 7,239,173 - Voogel July 3, 2	2007-07-03
Method of measuring performance of a semiconductor device and circuit for the same Grant 7,119,570 - Chirania , et al. October 10, 2	2006-10-10
Data monitoring for single event upset in a programmable logic device Grant 7,109,746 - Voogel , et al. September 19, 2	2006-09-19
Method and apparatus for voltage regulation within an integrated circuit Grant 7,109,783 - Kondapalli , et al. September 19, 2	2006-09-19
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Grant 7,110,281 - Voogel , et al. September 19, 2	2006-09-19
PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets Grant 7,064,574 - Voogel , et al. June 20, 2	2006-06-20
PLD lookup table including transistors of more than one oxide thickness Grant 7,053,654 - Young , et al. May 30, 2	2006-05-30
Single event upset in SRAM cells in FPGAs with high resistivity gate structures Grant 6,982,451 - Voogel , et al. January 3, 2	2006-01-03
Integrated circuit multiplexer including transistors of more than one oxide thickness Grant 6,949,951 - Young , et al. September 27, 2	2005-09-27
Single event upset in SRAM cells in FPGAs with leaky gate transistors Grant 6,822,894 - Costello , et al. November 23, 2	2004-11-23
PLD lookup table including transistors of more than one oxide thickness Grant 6,768,338 - Young , et al. July 27, 2	2004-07-27
Integrated circuit multiplexer including transistors of more than one oxide thickness Grant 6,768,335 - Young , et al. July 27, 2	2004-07-27
Method and apparatus for voltage regulation within an integrated circuit Grant 6,753,722 - Kondapalli , et al. June 22, 2	2004-06-22
Method and test circuit for developing integrated circuit fabrication processes Grant 6,621,289 - Voogel September 16, 2	2003-09-16
Non-volatile memory array using gate breakdown structures Grant 6,522,582 - Rao , et al. February 18, 2	2003-02-18
Redundancy architecture and method for non-volatile storage Grant 6,438,065 - Rao , et al. August 20, 2	2002-08-20
Method for fabricating PLDs including multiple discrete devices formed on a single chip Grant 6,362,651 - Voogel March 26, 2	2002-03-26
Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process Grant 6,243,294 - Rao , et al. June 5, 2	2001-06-05
One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS Grant 6,208,549 - Rao , et al. March 27, 2	2001-03-27
Layout architecture and method for fabricating PLDs including multiple discrete devices formed on a single chip Grant 6,157,213 - Voogel December 5, 2	2000-12-05
Decoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process Grant 6,055,205 - Rao , et al. April 25, 2	2000-04-25
Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process Grant 6,044,012 - Rao , et al. March 28, 2	2000-03-28
Antifuse with improved on-state reliability Grant 6,033,938 - Voogel , et al. March 7, 2	2000-03-07
DRAM configuration in PLDs Grant 5,986,958 - Voogel November 16, 1	1999-11-16
Triple-well silicon controlled rectifier with dynamic holding voltage Grant 5,959,821 - Voogel September 28, 1	1999-09-28
Non-volatile memory array using gate breakdown structure Grant 5,949,712 - Rao , et al. September 7, 1	1999-09-07
Pass gate circuit with body bias control Grant 5,880,620 - Gitlin , et al. March 9, 1	1999-03-09
Non-volatile storage for standard CMOS integrated circuits Grant 5,835,402 - Rao , et al. November 10, 1	1998-11-10

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