Von Thun; Matthew

Patent Applications and Registrations

Patent applications and USPTO patent grants for Von Thun; Matthew.The latest application filed is for "method for concurrent system management and error detection and correction requests in integrated circuits through location aware avoidance logic".

Company Profile

0.9.8

Von Thun; Matthew - Colorado Springs CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion Grant 9,647,205 - Popelar , et al. May 9, 2	2017-05-09
Method for concurrent system management and error detection and correction requests in integrated circuits through location aware avoidance logic Grant 9,519,442 - Mnich , et al. December 13, 2	2016-12-13
Method For Concurrent System Management And Error Detection And Correction Requests In Integrated Circuits Through Location Aware Avoidance Logic App 20160117223 - Mnich; Christopher ; et al.	2016-04-28
Integrated Circuit Shielding Technique Utilizing Stacked Die Technology Incorporating Top And Bottom Nickel-iron Alloy Shields Having A Low Coefficient Of Thermal Expansion App 20160056372 - Popelar; Scott ; et al.	2016-02-25
Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion Grant 9,209,138 - Popelar , et al. December 8, 2	2015-12-08
Independent orthogonal error correction and detection Grant 8,661,320 - Von Thun , et al. February 25, 2	2014-02-25
Independent Orthogonal Error Correction And Detection App 20130091405 - Von Thun; Matthew ; et al.	2013-04-11
Temperature insensitive reference circuit for use in a voltage detection circuit Grant 7,800,429 - Von Thun September 21, 2	2010-09-21
SET and SEGR resistant delay cell and delay line for Power-On Reset circuit applications Grant 7,733,146 - Von Thun June 8, 2	2010-06-08
Radiation hardened logic circuit Grant 7,423,448 - Von Thun September 9, 2	2008-09-09
Radiation hardened logic circuit App 20070205799 - Von Thun; Matthew	2007-09-06
SET and SEGR resistant delay cell and delay line for Power-On Reset circuit applications App 20070182474 - Von Thun; Matthew	2007-08-09
Temperature insensitive reference circuit for use in a voltage detection circuit App 20070170977 - Von Thun; Matthew	2007-07-26
Integrated inductor in semiconductor manufacturing Grant 6,614,093 - Ott , et al. September 2, 2	2003-09-02
Integrated inductor in semiconductor manufacturing App 20030109118 - Ott, George ; et al.	2003-06-12

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