| Patent | Date |
|---|
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Grant 10,978,452 - Chapman , et al. April 13, 2 | 2021-04-13 |
Structure And Method Of Latchup Robustness With Placement Of Through Wafer Via Within Cmos Circuitry
App 20190081046 - CHAPMAN; Phillip F. ; et al. | 2019-03-14 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Grant 10,170,476 - Chapman , et al. J | 2019-01-01 |
Structure, Method, And Circuit For Electrostatic Discharge Protection Utilizing A Rectifying Contact
App 20180358352 - VOLDMAN; Steven H | 2018-12-13 |
Structure And Method Of Latchup Robustness With Placement Of Through Wafer Via Within Cmos Circuitry
App 20180040619 - CHAPMAN; Phillip F. ; et al. | 2018-02-08 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Grant 9,842,838 - Chapman , et al. December 12, 2 | 2017-12-12 |
Structure And Method Of Latchup Robustness With Placement Of Through Wafer Via Within Cmos Circuitry
App 20160268258 - CHAPMAN; Phillip F. ; et al. | 2016-09-15 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Grant 9,397,010 - Chapman , et al. July 19, 2 | 2016-07-19 |
Structure And Method Of Latchup Robustness With Placement Of Through Wafer Via Within Cmos Circuitry
App 20160126147 - Chapman; Phillip F. ; et al. | 2016-05-05 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Grant 9,275,997 - Chapman , et al. March 1, 2 | 2016-03-01 |
Si and SiGeC on a buried oxide layer on a substrate
Grant 9,087,925 - Liu , et al. July 21, 2 | 2015-07-21 |
Structure, structure and method of latch-up immunity for high and low voltage integrated circuits
Grant 8,994,026 - Voldman March 31, 2 | 2015-03-31 |
ESD network circuit with a through wafer via structure and a method of manufacture
Grant 8,962,480 - Voldman February 24, 2 | 2015-02-24 |
Structure, structure and method of latch-up immunity for high and low voltage integrated circuits
Grant 8,963,158 - Voldman February 24, 2 | 2015-02-24 |
Lateral diffusion field effect transistor with drain region self-aligned to gate electrode
Grant 8,946,013 - Feilchenfeld , et al. February 3, 2 | 2015-02-03 |
Structure And Method Of Latchup Robustness With Placement Of Through Wafer Via Within Cmos Circuitry
App 20140367792 - CHAPMAN; Phillip F. ; et al. | 2014-12-18 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Grant 8,853,789 - Chapman , et al. October 7, 2 | 2014-10-07 |
Design Structure, Structure And Method Of Latch-up Immunity For High And Low Voltage Integrated Circuits
App 20130299915 - VOLDMAN; Steven H. | 2013-11-14 |
Structure, structure and method of latch-up immunity for high and low voltage integrated circuits
Grant 8,519,402 - Voldman August 27, 2 | 2013-08-27 |
Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications
Grant 8,487,379 - Levy , et al. July 16, 2 | 2013-07-16 |
Design Structure, Structure And Method Of Latch-up Immunity For High And Low Voltage Integrated Circuits
App 20130168818 - VOLDMAN; Steven H. | 2013-07-04 |
Structure And Method Of Latchup Robustness With Placement Of Through Wafer Via Within Cmos Circuitry
App 20130154024 - CHAPMAN; Phillip F. ; et al. | 2013-06-20 |
Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors
Grant 8,423,936 - Voldman April 16, 2 | 2013-04-16 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Grant 8,420,518 - Chapman , et al. April 16, 2 | 2013-04-16 |
Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact
Grant 8,410,534 - Voldman April 2, 2 | 2013-04-02 |
Structure and method for latchup improvement using through wafer via latchup guard ring
Grant 8,390,074 - Voldman March 5, 2 | 2013-03-05 |
Optimized scheduling based on sensitivity data
Grant 8,301,288 - Denton , et al. October 30, 2 | 2012-10-30 |
Esd Network Circuit With A Through Wafer Via Structure And A Method Of Manufacture
App 20120238069 - VOLDMAN; Steven H. | 2012-09-20 |
Structure And Method For Buried Inductors For Ultra-high Resistivity Wafers For Soi/rf Sige Applications
App 20120205741 - LEVY; Max G. ; et al. | 2012-08-16 |
ESD network circuit with a through wafer via structure and a method of manufacture
Grant 8,232,625 - Voldman July 31, 2 | 2012-07-31 |
Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation
Grant 8,227,318 - Levy , et al. July 24, 2 | 2012-07-24 |
Integrated Circuit Structures With Silicon Germanium Film Incorporated As Local Interconnect And/or Contact
App 20120132974 - Voldman; Steven H. | 2012-05-31 |
Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications
Grant 8,188,570 - Levy , et al. May 29, 2 | 2012-05-29 |
Lateral Diffusion Field Effect Transistor With Drain Region Self-aligned To Gate Electrode
App 20120126319 - Feilchenfeld; Natalie B. ; et al. | 2012-05-24 |
Semiconductor Structure And Method Of Designing Semiconductor Structure To Avoid High Voltage Initiated Latch-up In Low Voltage Sectors
App 20120124533 - VOLDMAN; Steven H. | 2012-05-17 |
Integrated circuit structure incorporating an inductor, an associated design method and an associated design system
Grant 8,171,435 - He , et al. May 1, 2 | 2012-05-01 |
Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology
Grant 8,138,579 - Liu , et al. March 20, 2 | 2012-03-20 |
Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact
Grant 8,129,772 - Voldman March 6, 2 | 2012-03-06 |
Lateral diffusion field effect transistor with drain region self-aligned to gate electrode
Grant 8,114,750 - Feilchenfeld , et al. February 14, 2 | 2012-02-14 |
Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors
Grant 8,108,817 - Voldman January 31, 2 | 2012-01-31 |
Deep trench based far subcollector reachthrough
Grant 8,105,924 - Orner , et al. January 31, 2 | 2012-01-31 |
Methodology for placement based on circuit function and latchup sensitivity
Grant 8,108,822 - Voldman January 31, 2 | 2012-01-31 |
Electrostatic discharge structures and methods of manufacture
Grant 8,054,597 - Gebreselasie , et al. November 8, 2 | 2011-11-08 |
Product and method for integration of deep trench mesh and structures under a bond pad
Grant 8,044,510 - Gebreselasie , et al. October 25, 2 | 2011-10-25 |
Semiconductor devices
Grant 8,035,190 - Liu , et al. October 11, 2 | 2011-10-11 |
Structures And Methods Of Forming Sige And Sigec Buried Layer For Soi/sige Technology
App 20110227130 - LIU; Xuefeng ; et al. | 2011-09-22 |
Structure And Method For Latchup Improvement Using Through Wafer Via Latchup Guard Ring
App 20110227166 - VOLDMAN; Steven H. | 2011-09-22 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Grant 8,017,471 - Chapman , et al. September 13, 2 | 2011-09-13 |
Structures for electrostatic discharge protection for bipolar semiconductor circuitry
Grant 8,015,518 - Voldman September 6, 2 | 2011-09-06 |
Design structure with a deep sub-collector, a reach-through structure and trench isolation
Grant 8,015,538 - Coolbaugh , et al. September 6, 2 | 2011-09-06 |
Structure And Method Of Latchup Robustness With Placement Of Through Wafer Via Within Cmos Circuitry
App 20110198703 - CHAPMAN; Phillip F. ; et al. | 2011-08-18 |
Structure and method for latchup improvement using through wafer via latchup guard ring
Grant 7,989,282 - Voldman August 2, 2 | 2011-08-02 |
Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate
Grant 7,989,306 - Liu , et al. August 2, 2 | 2011-08-02 |
Wrapped gate junction field effect transistor
Grant 7,977,714 - Ellis-Monaghan , et al. July 12, 2 | 2011-07-12 |
Lateral diffusion field effect transistor with a trench field plate
Grant 7,956,412 - Feilchenfeld , et al. June 7, 2 | 2011-06-07 |
High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature
Grant 7,949,983 - Eshun , et al. May 24, 2 | 2011-05-24 |
Integration of Multiple Gate Oxides with Shallow Trench Isolation Methods to Minimize Divot Formation
App 20110117714 - Levy; Max ; et al. | 2011-05-19 |
Apparatus and method for electronic fuse with improved ESD tolerance
Grant 7,943,437 - Voldman May 17, 2 | 2011-05-17 |
Modifying layout of IC based on function of interconnect and related circuit and design structure
Grant 7,886,240 - Adkisson , et al. February 8, 2 | 2011-02-08 |
Vertical parallel plate capacitor structures
Grant 7,876,547 - Gebreselasie , et al. January 25, 2 | 2011-01-25 |
Design Structure And Method For Buried Inductors For Ultra-high Resistivity Wafers For Soi/rf Sige Applications
App 20100327398 - LEVY; Max G. ; et al. | 2010-12-30 |
Electrostatic Discharge Structures and Methods of Manufacture
App 20100321842 - GEBRESELASIE; Ephrem G. ; et al. | 2010-12-23 |
Structure and method for latchup suppression
Grant 7,855,104 - Voldman December 21, 2 | 2010-12-21 |
Structure for a latchup robust array I/O using through wafer via
Grant 7,855,420 - Chapman , et al. December 21, 2 | 2010-12-21 |
Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications
Grant 7,842,580 - Levy , et al. November 30, 2 | 2010-11-30 |
Structure for low capacitance ESD robust diodes
Grant 7,821,099 - Voldman October 26, 2 | 2010-10-26 |
Dendrite growth control circuit
Grant 7,807,562 - Hershberger , et al. October 5, 2 | 2010-10-05 |
Esd Network Circuit With A Through Wafer Via Structure And A Method Of Manufacture
App 20100244187 - VOLDMAN; Steven H. | 2010-09-30 |
Integrated Circuit Structures With Silicon Germanium Film Incorporated As Local Interconnect And/or Contact
App 20100244112 - Voldman; Steven H. | 2010-09-30 |
Structure And Method For Latchup Improvement Using Through Wafer Via Latchup Guard Ring
App 20100244179 - VOLDMAN; Steven H. | 2010-09-30 |
Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact
Grant 7,800,184 - Voldman September 21, 2 | 2010-09-21 |
Semiconductor devices
Grant 7,755,161 - Liu , et al. July 13, 2 | 2010-07-13 |
Integrated Circuit Structure Incorporating An Inductor, An Associated Design Method And An Associated Design System
App 20100175035 - He; Zhong-Xiang ; et al. | 2010-07-08 |
Semiconductor Devices
App 20100171148 - LIU; Xuefeng ; et al. | 2010-07-08 |
Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit
Grant 7,750,408 - He , et al. July 6, 2 | 2010-07-06 |
Method Of Interconnect Checking And Verification For Multiple Electrostatic Discharge Specifications
App 20100161304 - VOLDMAN; Steven H. | 2010-06-24 |
Latchup robust array I/O using through wafer via
Grant 7,741,681 - Chapman , et al. June 22, 2 | 2010-06-22 |
Vertical P-N junction device and method of forming same
Grant 7,732,835 - Voegeli , et al. June 8, 2 | 2010-06-08 |
Tunable semiconductor diodes
Grant 7,732,293 - Voldman June 8, 2 | 2010-06-08 |
Semiconductor structure and method of manufacture
Grant 7,718,481 - Liu , et al. May 18, 2 | 2010-05-18 |
Deep Trench Based Far Subcollector Reachthrough
App 20100117189 - Orner; Bradley A. ; et al. | 2010-05-13 |
Methodology for automated design of vertical parallel plate capacitors
Grant 7,698,678 - Voldman April 13, 2 | 2010-04-13 |
Structure for a latchup robust gate array using through wafer via
Grant 7,696,541 - Chapman , et al. April 13, 2 | 2010-04-13 |
Deep trench based far subcollector reachthrough
Grant 7,691,734 - Orner , et al. April 6, 2 | 2010-04-06 |
Resistor ballasted transistors
Grant 7,671,423 - Voldman March 2, 2 | 2010-03-02 |
Structure And Method Of Latchup Robustness With Placement Of Through Wafer Via Within Cmos Circuitry
App 20100032767 - Chapman; Phillip F. ; et al. | 2010-02-11 |
Design Structure, Structure And Method Of Latch-up Immunity For High And Low Voltage Integrated Circuits
App 20100025761 - Voldman; Steven H. | 2010-02-04 |
Design Structure and Method for Buried Inductors for Ultra-High Resistivity Wafers for SOI/RF SIGE Applications
App 20090283854 - Levy; Max G. ; et al. | 2009-11-19 |
Lateral Diffusion Field Effect Transistor With Drain Region Self-aligned To Gate Electrode
App 20090261426 - Feilchenfeld; Natalie B. ; et al. | 2009-10-22 |
Electro-static discharge protection circuit
Grant 7,606,013 - Ellis-Monaghan , et al. October 20, 2 | 2009-10-20 |
Semiconductor devices
Grant 7,582,949 - Liu , et al. September 1, 2 | 2009-09-01 |
Semiconductor Structure and Method of Designing Semiconductor Structure to Avoid High Voltage Initiated Latch-up in Low Voltage Sectors
App 20090210833 - Voldman; Steven H. | 2009-08-20 |
Modifying Layout Of Ic Based On Function Of Interconnect And Related Circuit And Design Structure
App 20090193378 - Adkisson; James W. ; et al. | 2009-07-30 |
Resistor Ballasted Transistors
App 20090179276 - Voldman; Steven H. | 2009-07-16 |
Charge modulation network for multiple power domains for silicon-on-insulator technology
Grant 7,560,778 - Cain , et al. July 14, 2 | 2009-07-14 |
Design Methodology For Guard Ring Design Resistance Optimization For Latchup Prevention
App 20090166798 - Chapman; Phillip F. ; et al. | 2009-07-02 |
Electrostatic Discharge Protection For Bipolar Semiconductor Circuitry
App 20090152680 - Voldman; Steven H. | 2009-06-18 |
Design Structures For Electrostatic Discharge Protection For Bipolar Semiconductor Circuitry
App 20090154037 - Voldman; Steven H. | 2009-06-18 |
Structure For A Latchup Robust Gate Array Using Through Wafer Via
App 20090152593 - Chapman; Phillip Francis ; et al. | 2009-06-18 |
Structure For A Latchup Robust Array I/o Using Through Wafer Via
App 20090152592 - Chapman; Phillip Francis ; et al. | 2009-06-18 |
Latchup Robust Array I/o Using Through Wafer Via
App 20090152632 - Chapman; Phillip Francis ; et al. | 2009-06-18 |
Design methodology of guard ring design resistance optimization for latchup prevention
Grant 7,549,135 - Chapman , et al. June 16, 2 | 2009-06-16 |
Lateral Diffusion Field Effect Transistor With A Trench Field Plate
App 20090140343 - Feilchenfeld; Natalie B. ; et al. | 2009-06-04 |
Semiconductor devices
Grant 7,538,409 - Liu , et al. May 26, 2 | 2009-05-26 |
Product And Method For Integration Of Deep Trench Mesh And Structures Under A Bond Pad
App 20090127628 - GEBRESELASIE; Ephrem G. ; et al. | 2009-05-21 |
Inter-chip ESD protection structure for high speed and high frequency devices
Grant 7,535,105 - Voldman May 19, 2 | 2009-05-19 |
Design Structure Incorporating Vertical Parallel Plate Capacitor Structures
App 20090102016 - Gebreselasie; Ephrem G. ; et al. | 2009-04-23 |
Wrapped Gate Junction Field Effect Transistor
App 20090101941 - Ellis-Monaghan; John ; et al. | 2009-04-23 |
Interconnect structure encased with high and low k interlevel dielectrics
Grant 7,521,359 - Voldman April 21, 2 | 2009-04-21 |
Dual Work Function High Voltage Devices
App 20090090983 - Adkisson; James W. ; et al. | 2009-04-09 |
Methodology For Placement Based On Circuit Function And Latchup Sensitivity
App 20090070718 - VOLDMAN; Steven H. | 2009-03-12 |
Latchup robust gate array using through wafer via
Grant 7,498,622 - Chapman , et al. March 3, 2 | 2009-03-03 |
Semiconductor Devices
App 20090039385 - LIU; Xuefeng ; et al. | 2009-02-12 |
Dendrite Growth Control Circuit
App 20090035933 - Hershberger; Douglas B. ; et al. | 2009-02-05 |
Through via in ultra high resistivity wafer and related methods
Grant 7,485,965 - Lanzerotti , et al. February 3, 2 | 2009-02-03 |
Product and method for integration of deep trench mesh and structures under a bond pad
Grant 7,482,258 - Gebreselasie , et al. January 27, 2 | 2009-01-27 |
High Tolerance Tcr Balanced High Current Resistor For Rf Cmos And Rf Sige Bicmos Applications And Cadenced Based Hierarchical Parameterized Cell Design Kit With Tunable Tcr And Esd Resistor Ballasting Feature
App 20090019414 - Eshun; Ebenezer E. ; et al. | 2009-01-15 |
Apparatus for electrostatic discharge protection of bipolar emitter follower circuits
Grant 7,477,497 - Botula , et al. January 13, 2 | 2009-01-13 |
Dendrite growth control circuit
Grant 7,473,643 - Hershberger , et al. January 6, 2 | 2009-01-06 |
Structures And Methods Of Forming Sige And Sigec Buried Layer For Soi/sige Technology
App 20090001414 - Liu; Xuefeng ; et al. | 2009-01-01 |
Structures And Methods Of Forming Sige And Sigec Buried Layer For Soi/sige Technology
App 20090001417 - LIU; Xuefeng ; et al. | 2009-01-01 |
Tunable Semiconductor Diodes
App 20080311723 - Voldman; Steven H. | 2008-12-18 |
Vertical Parallel Plate Capacitor Structures
App 20080297975 - Gebreselasie; Ephrem G. ; et al. | 2008-12-04 |
Methodology For Automated Design Of Vertical Parallel Plate Capacitors
App 20080301592 - Voldman; Steven H. | 2008-12-04 |
Method of forming a vertical P-N junction device
Grant 7,459,367 - Voegeli , et al. December 2, 2 | 2008-12-02 |
Through Via In Ultra High Resistivity Wafer And Related Methods
App 20080290524 - Lanzerotti; Louis D. ; et al. | 2008-11-27 |
Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof
Grant 7,445,966 - Ellis-Monaghan , et al. November 4, 2 | 2008-11-04 |
Structure And Method For Enhanced Triple Well Latchup Robustness
App 20080265333 - Collins; David S. ; et al. | 2008-10-30 |
Structure and method for enhanced triple well latchup robustness
Grant 7,442,996 - Collins , et al. October 28, 2 | 2008-10-28 |
Vertical P-n Junction Device And Method Of Forming Same
App 20080258173 - Voegeli; Benjamin T. ; et al. | 2008-10-23 |
Tunable semiconductor diodes
Grant 7,439,145 - Voldman October 21, 2 | 2008-10-21 |
Apparatus And Method For Electronic Fuse With Improved Esd Tolerance
App 20080254609 - VOLDMAN; Steven H. | 2008-10-16 |
Method And Structure For Low Capacitance Esd Robust Diodes
App 20080251846 - Voldman; Steven H. | 2008-10-16 |
Integrated Circuit Stucture Incorporating An Inductor, An Associated Design Method And An Associated Design System
App 20080237789 - He; Zhong-Xiang ; et al. | 2008-10-02 |
High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature
Grant 7,427,551 - Eshun , et al. September 23, 2 | 2008-09-23 |
Deep Trench Based Far Subcollector Reachthrough
App 20080211064 - Orner; Bradley A. ; et al. | 2008-09-04 |
Interconnect structure encased with high and low k interlevel dielectrics
Grant 7,411,305 - Voldman August 12, 2 | 2008-08-12 |
INTERCONNECT STRUCTURE ENCASED WITH HIGH AND LOW k INTERLEVEL DIELECTRICS
App 20080169572 - Voldman; Steven H. | 2008-07-17 |
Methodology for placement based on circuit function and latchup sensitivity
Grant 7,401,311 - Voldman July 15, 2 | 2008-07-15 |
Radiation Tolerant Electrostatic Discharge Protection Networks
App 20080158747 - Voldman; Steven H. | 2008-07-03 |
Electro-Static Discharge Protection Circuit
App 20080144240 - Ellis-Monaghan; John J. ; et al. | 2008-06-19 |
Modulated Trigger Device
App 20080135941 - Voldman; Steven H. ; et al. | 2008-06-12 |
Method of forming low capacitance ESD robust diodes
Grant 7,384,854 - Voldman June 10, 2 | 2008-06-10 |
Design Methodology Of Guard Ring Design Resistance Optimization For Latchup Prevention
App 20080134104 - Chapman; Phillip F. ; et al. | 2008-06-05 |
Method Of Forming Guard Ring Parameterized Cell Structure In A Hierarchical Parameterized Cell Design, Checking And Verification System
App 20080098337 - Perez; Charles N. ; et al. | 2008-04-24 |
Semiconductor Structure And Method Of Manufacture
App 20080092094 - COOLBAUGH; Douglas D. ; et al. | 2008-04-17 |
Semiconductor Structure And Method Of Manufacture
App 20080087978 - Coolbaugh; Douglas D. ; et al. | 2008-04-17 |
Radiation tolerant electrostatic discharge protection networks
Grant 7,358,572 - Voldman April 15, 2 | 2008-04-15 |
Electrostatic discharge protection networks for triple well semiconductor devices
Grant 7,348,657 - Pequignot , et al. March 25, 2 | 2008-03-25 |
Modulated trigger device
Grant 7,348,251 - Voldman , et al. March 25, 2 | 2008-03-25 |
Method of displaying a guard ring within an integrated circuit
Grant 7,350,160 - Perez , et al. March 25, 2 | 2008-03-25 |
Method of making an electronic fuse with improved ESD tolerance
Grant 7,334,320 - Voldman February 26, 2 | 2008-02-26 |
Semiconductor Devices
App 20080036029 - LIU; Xuefeng ; et al. | 2008-02-14 |
Esd Power Clamp In Triple Well
App 20080029824 - Baizley; Arnold E. ; et al. | 2008-02-07 |
High Voltage Electrostatic Discharge Protection Devices And Electrostatic Discharge Protection Circuits
App 20080023767 - Voldman; Steven H. | 2008-01-31 |
Power Clamp Devices With Vertical Npn Devices
App 20080002316 - Adkisson; James W. ; et al. | 2008-01-03 |
Apparatus For Electrostatic Discharge Protection Of Bipolar Emitter Follower Circuits
App 20070297107 - Botula; Alan B. ; et al. | 2007-12-27 |
Semiconductor devices
App 20070287243 - Liu; Xuefeng ; et al. | 2007-12-13 |
Semiconductor device and method having multiple subcollectors formed on a common wafer
Grant 7,303,968 - Dunn , et al. December 4, 2 | 2007-12-04 |
Integrated Circuit Protection From Esd Damage During Fabrication
App 20070262305 - Adkisson; James W. ; et al. | 2007-11-15 |
Structure And Method For Latchup Suppression
App 20070259490 - VOLDMAN; Steven H. | 2007-11-08 |
Semiconductor Structure And Method Of Manufacture
App 20070241421 - Liu; Xuefeng ; et al. | 2007-10-18 |
Structure and method for latchup suppression
Grant 7,282,771 - Voldman October 16, 2 | 2007-10-16 |
Structure And Method For Latchup Suppression
App 20070228487 - VOLDMAN; Steven H. | 2007-10-04 |
Structure And Method For Latchup Suppression
App 20070215953 - VOLDMAN; STEVEN H. | 2007-09-20 |
Method And Structure Of Refractory Metal Reach Through In Bipolar Transistor
App 20070205430 - Collins; David S. ; et al. | 2007-09-06 |
Integrated Circuit Structures With Silicon Germanium Film Incorporated As Local Interconnect And/or Contact
App 20070181972 - Voldman; Steven H. | 2007-08-09 |
Structure And Method For Enhanced Triple Well Latchup Robustness
App 20070170515 - Collins; David S. ; et al. | 2007-07-26 |
Semiconductor structure
Grant 7,242,071 - Liu , et al. July 10, 2 | 2007-07-10 |
Silicon germanium heterojunction bipolar transistor with carbon incorporation
Grant 7,202,136 - Lanzerotti , et al. April 10, 2 | 2007-04-10 |
Radiation Tolerant Electrostatic Discharge Protection Networks
App 20070075373 - Voldman; Steven H. | 2007-04-05 |
Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip
Grant 7,200,825 - Watson , et al. April 3, 2 | 2007-04-03 |
Inter-chip Esd Protection Structure For High Speed And High Frequency Devices
App 20070029646 - Voldman; Steven H. | 2007-02-08 |
Lateral lubistor structure and method
Grant 7,173,310 - Voldman , et al. February 6, 2 | 2007-02-06 |
Vertical P-n Junction Device And Method Of Forming Same
App 20070023811 - Voegeli; Benjamin T. ; et al. | 2007-02-01 |
Structure and method for local resistor element in integrated circuit technology
Grant 7,166,904 - Gill , et al. January 23, 2 | 2007-01-23 |
Charge modulation network for multiple power domains for silicon-on-insulator technology
App 20070008668 - Cain; David A. ; et al. | 2007-01-11 |
Tunable Semiconductor Diodes
App 20070004160 - Voldman; Steven H. | 2007-01-04 |
Lateral Lubistor Structure And Method
App 20060273372 - Voldman; Steven H. ; et al. | 2006-12-07 |
Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices
App 20060267101 - Pequignot; James P. ; et al. | 2006-11-30 |
Dendrite Growth Control Circuit
App 20060264026 - Hershberger; Douglas B. ; et al. | 2006-11-23 |
Electrostatic discharge protection networks for triple well semiconductor devices
Grant 7,138,701 - Pequignot , et al. November 21, 2 | 2006-11-21 |
Silicon germanium heterojunction bipolar transistor with carbon incorporation
Grant 7,138,669 - Lanzerotti , et al. November 21, 2 | 2006-11-21 |
Tunable ESD trigger and power clamp circuit
Grant 7,136,268 - Stricker , et al. November 14, 2 | 2006-11-14 |
INTERCONNECT STRUCTURE ENCASED WITH HIGH AND LOW k INTERLEVEL DIELECTRICS
App 20060249787 - Voldman; Steven H. | 2006-11-09 |
ESD design, verification and checking system and method of use
Grant 7,134,099 - Collins , et al. November 7, 2 | 2006-11-07 |
Product And Method For Integration Of Deep Trench Mesh And Structures Under A Bond Pad
App 20060246682 - Gebreselasie; Ephrem G. ; et al. | 2006-11-02 |
Charge modulation network for multiple power domains for silicon-on-insulator technology
Grant 7,129,545 - Cain , et al. October 31, 2 | 2006-10-31 |
Method And Structure For Ion Implantation By Ion Scattering
App 20060234484 - Lanzerotti; Louis D. ; et al. | 2006-10-19 |
Tunable semiconductor diodes
Grant 7,119,401 - Voldman October 10, 2 | 2006-10-10 |
Dendrite growth control circuit
Grant 7,109,584 - Hershberger , et al. September 19, 2 | 2006-09-19 |
Apparatus and method for electronic fuse with improved ESD tolerance
Grant 7,106,164 - Voldman September 12, 2 | 2006-09-12 |
Method, apparatus and circuit for latchup suppression in a gate-array ASIC environment
Grant 7,102,867 - Voldman September 5, 2 | 2006-09-05 |
Apparatus And Method For Controlling Leakage Current In Bipolar Esd Clamping Devices
App 20060187595 - Botula; Alan B. ; et al. | 2006-08-24 |
Charge Modulation Network For Multiple Power Domains For Silicon-on-insulator Technology
App 20060187596 - Cain; David A. ; et al. | 2006-08-24 |
Methodology for placement based on circuit function and latchup sensitivity
Grant 7,089,520 - Voldman August 8, 2 | 2006-08-08 |
Methodology For Placement Based On Circuit Function And Latchup Sensitivity
App 20060166426 - VOLDMAN; Steven H. | 2006-07-27 |
Semiconductor device and method having multiple subcollectors formed on a common wafer
App 20060157824 - Dunn; James S. ; et al. | 2006-07-20 |
Dual chip stack method for electro-static discharge protection of integrated circuits
Grant 7,067,914 - Malinowski , et al. June 27, 2 | 2006-06-27 |
Semiconductor device and method having multiple subcollectors formed on a common wafer
Grant 7,064,416 - Dunn , et al. June 20, 2 | 2006-06-20 |
Dendrite Growth Control Circuit
App 20060110909 - Hershberger; Douglas B. ; et al. | 2006-05-25 |
Method and structure for improving latch-up immunity using non-dopant implants
Grant 7,041,581 - Voldman , et al. May 9, 2 | 2006-05-09 |
Methodology Of Quantification Of Transmission Probability For Minority Carrier Collection In A Semiconductor Chip
App 20060048080 - Watson; Anne E. ; et al. | 2006-03-02 |
Latch-up analysis and parameter modification
Grant 6,996,786 - Voldman February 7, 2 | 2006-02-07 |
Modulated trigger device
App 20050280093 - Voldman, Steven H. ; et al. | 2005-12-22 |
Optimized Scheduling Based On Sensitivity Data
App 20050283265 - Denton, Brian T. ; et al. | 2005-12-22 |
Modulated trigger device
Grant 6,975,015 - Voldman , et al. December 13, 2 | 2005-12-13 |
High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature
Grant 6,969,903 - Eshun , et al. November 29, 2 | 2005-11-29 |
Silicon germanium heterojunction bipolar transistor with carbon incorporation
App 20050233534 - Lanzerotti, Louis D. ; et al. | 2005-10-20 |
Structure and method for latchup suppression utilizing trench and masked sub-collector implantation
Grant 6,956,266 - Voldman , et al. October 18, 2 | 2005-10-18 |
Tunable Esd Trigger And Power Clamp Circuit
App 20050225910 - Stricker, Andreas D. ; et al. | 2005-10-13 |
High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature
App 20050221572 - Eshun, Ebenezer E. ; et al. | 2005-10-06 |
Method And Application Of Pica (picosecond Imaging Circuit Analysis) For High Current Pulsed Phenomena
App 20050218921 - Sanda, Naoko Pia ; et al. | 2005-10-06 |
Electrostatic discharge input and power clamp circuit for high cutoff frequency technology radio frequency (RF) applications
Grant 6,946,707 - Voldman September 20, 2 | 2005-09-20 |
Method and application of PICA (picosecond imaging circuit analysis) for high current pulsed phenomena
Grant 6,943,578 - Sanda , et al. September 13, 2 | 2005-09-13 |
Structure And Method For Local Resistor Element In Integrated Circuit Technology
App 20050167786 - Gill, Jason P. ; et al. | 2005-08-04 |
Electrostatic Discharge Input And Power Clamp Circuit For High Cutoff Frequency Technology Radio Frequency (rf) Applications
App 20050161743 - Voldman, Steven H. | 2005-07-28 |
HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SiGe BiCMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE
App 20050156281 - Eshun, Ebenezer E. ; et al. | 2005-07-21 |
Tunable Semiconductor Diodes
App 20050151223 - Voldman, Steven H. | 2005-07-14 |
Apparatus And Method For Electronic Fuse With Improved Esd Tolerance
App 20050127475 - Voldman, Steven H. | 2005-06-16 |
Modulated Trigger Device
App 20050121702 - Voldman, Steven H. ; et al. | 2005-06-09 |
Apparatus and method for electronic fuse with improved ESD tolerance
App 20050121741 - Voldman, Steven H. | 2005-06-09 |
Methodology For Placement Based On Circuit Function And Latchup Sensitivity
App 20050108670 - Voldman, Steven H. | 2005-05-19 |
System and method for VLSI visualization
Grant 6,895,372 - Knebel , et al. May 17, 2 | 2005-05-17 |
Esd Design, Verification And Checking System And Method Of Use
App 20050102644 - Collins, David S. ; et al. | 2005-05-12 |
Electrostatic discharge protection networks for triple well semiconductor devices
Grant 6,891,207 - Pequignot , et al. May 10, 2 | 2005-05-10 |
Carbon-modulated breakdown voltage SiGe transistor for low voltage trigger ESD applications
Grant 6,878,976 - Coolbaugh , et al. April 12, 2 | 2005-04-12 |
Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices
App 20050073006 - Pequignot, James P. ; et al. | 2005-04-07 |
Silicon germanium heterojunction bipolar transistor with carbon incorporation
App 20050051798 - Lanzerotti, Louis D. ; et al. | 2005-03-10 |
Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure
Grant 6,838,323 - Gauthier , et al. January 4, 2 | 2005-01-04 |
A Method, Apparatus And Circuit For Latchup Suppression In A Gate-array Asic Environment
App 20040262643 - Voldman, Steven H. | 2004-12-30 |
Method Of Forming Guard Ring Parameterized Cell Structure In A Hierarchical Parameterized Cell Design, Checking And Verification System
App 20040268284 - Perez, Charles N. ; et al. | 2004-12-30 |
Method and structure for improving latch-up immunity using non-dopant implants
App 20040219769 - Voldman, Steven H. ; et al. | 2004-11-04 |
Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices
App 20040135141 - Pequignot, James P ; et al. | 2004-07-15 |
Method And Structure For Forming Precision Mim Fusible Circuit Elements Using Fuses And Antifuses
App 20040115875 - Voldman, Steven H. ; et al. | 2004-06-17 |
Halo-free non-rectifying contact on chip with halo source/drain diffusion
Grant 6,750,109 - Culp , et al. June 15, 2 | 2004-06-15 |
Post-fuse blow corrosion prevention structure for copper fuses
Grant 6,746,947 - Daubenspeck , et al. June 8, 2 | 2004-06-08 |
Dual emitter transistor with ESD protection
Grant 6,731,488 - Voldman May 4, 2 | 2004-05-04 |
Method of automated design and checking for ESD robustness
Grant 6,725,439 - Homsinger , et al. April 20, 2 | 2004-04-20 |
Automated hierarchical parameterized ESD network design and checking system
Grant 6,704,179 - Voldman March 9, 2 | 2004-03-09 |
Tungsten hot wire current limiter for ESD protection
Grant 6,700,164 - Brennan , et al. March 2, 2 | 2004-03-02 |
SOI voltage-tolerant body-coupled pass transistor
App 20040021502 - Voldman, Steven H. | 2004-02-05 |
Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses
Grant 6,680,520 - Voldman , et al. January 20, 2 | 2004-01-20 |
Silicon germanium heterojunction bipolar transistor with carbon incorporation
Grant 6,670,654 - Lanzerotti , et al. December 30, 2 | 2003-12-30 |
Dual emitter transistor with ESD protection
App 20030184943 - Voldman, Steven H. | 2003-10-02 |
SOI voltage-tolerant body-coupled pass transistor
Grant 6,628,159 - Voldman September 30, 2 | 2003-09-30 |
Carbon-modulated breakdown voltage SiGe transistor for low voltage trigger ESD applications
App 20030173580 - Coolbaugh, Douglas D. ; et al. | 2003-09-18 |
Method and structure for low capacitance ESD robust diodes
App 20030168701 - Voldman, Steven H. | 2003-09-11 |
Automated hierarchical parameterized ESD network design and checking system
App 20030147187 - Voldman, Steven H. | 2003-08-07 |
Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity
Grant 6,600,199 - Voldman , et al. July 29, 2 | 2003-07-29 |
Silicon germanium heterojunction bipolar transistor with carbon incorporation
App 20030129802 - Lanzerotti, Louis D. ; et al. | 2003-07-10 |
Self-aligned silicon germanium heterojunction bipolar transistor device with electrostatic discharge crevice cover for salicide displacement
Grant 6,586,818 - Voldman July 1, 2 | 2003-07-01 |
Post-fuse blow corrosion prevention structure for copper fuses
App 20030116820 - Daubenspeck, Timothy H. ; et al. | 2003-06-26 |
Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure
App 20030102513 - Gauthier, Robert J. ; et al. | 2003-06-05 |
Method and apparatus for providing electrostatic discharge protection of a magnetic head using a mechanical switch and an electrostatic discharge device network
Grant 6,574,078 - Voldman June 3, 2 | 2003-06-03 |
Semiconductor device and method having multiple subcollectors formed on a common wafer
App 20030094673 - Dunn, James S. ; et al. | 2003-05-22 |
Dual chip stack method for electro-static discharge protection of integrated circuits
App 20030089979 - Malinowski, John C. ; et al. | 2003-05-15 |
Integrated high-performance decoupling capacitor and heat sink
Grant 6,548,338 - Bernstein , et al. April 15, 2 | 2003-04-15 |
Method and apparatus for providing ESD protection for receiver networks
App 20030067726 - Voldman, Steven H. | 2003-04-10 |
Dual buried oxide film SOI structure and method of manufacturing the same
Grant 6,531,741 - Hargrove , et al. March 11, 2 | 2003-03-11 |
Method for evaluating circuit design for ESD electrostatic discharge robustness
Grant 6,526,548 - Voldman February 25, 2 | 2003-02-25 |
Semiconductor structure having heterogenous silicide regions having titanium and molybdenum
Grant 6,512,296 - Gauthier, Jr. , et al. January 28, 2 | 2003-01-28 |
Post-fuse blow corrosion prevention structure for copper fuses
Grant 6,498,385 - Daubenspeck , et al. December 24, 2 | 2002-12-24 |
Halo-free non-rectifying contact on chip with halo source/drain diffusion
App 20020149058 - Culp, James A. ; et al. | 2002-10-17 |
SOI devices with integrated gettering structure
App 20020140030 - Mandelman, Jack A. ; et al. | 2002-10-03 |
Internally ballasted silicon germanium transistor
Grant 6,455,919 - Brennan , et al. September 24, 2 | 2002-09-24 |
Internally Ballasted Silicon Germanium Transistor
App 20020130392 - Brennan, Ciaran J. ; et al. | 2002-09-19 |
MOSFET with lateral resistor ballasting
Grant 6,441,410 - Gauthier, Jr. , et al. August 27, 2 | 2002-08-27 |
Method and structure of a precision mim fusible circuit elements using fuses and antifuses
App 20020113297 - Voldman, Steven H. ; et al. | 2002-08-22 |
Double-gate low power SOI active clamp network for single power supply and multiple power supply applications
Grant 6,433,609 - Voldman August 13, 2 | 2002-08-13 |
Method for improved passive thermal flow in silicon on insulator devices
Grant 6,432,809 - Tonti , et al. August 13, 2 | 2002-08-13 |
Structure And Process For Multi-chip Chip Attach With Reduced Risk Of Electrostatic Discharge Damage
App 20020106893 - Furukawa, Toshiharu ; et al. | 2002-08-08 |
Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage
Grant 6,429,045 - Furukawa , et al. August 6, 2 | 2002-08-06 |
Halo-free non-rectifying contact on chip with halo source/drain diffusion
Grant 6,429,482 - Culp , et al. August 6, 2 | 2002-08-06 |
Asymmetrical semiconductor device for ESD protection
Grant 6,420,761 - Gauthier, Jr. , et al. July 16, 2 | 2002-07-16 |
Transistor having raised source and drain
Grant 6,420,766 - Brown , et al. July 16, 2 | 2002-07-16 |
Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity
App 20020084506 - Voldman, Steven H. ; et al. | 2002-07-04 |
Substrate pumped ESD network with trench structure
Grant 6,411,480 - Gauthier , et al. June 25, 2 | 2002-06-25 |
Low power SOI ESD buffer driver networks having dynamic threshold MOSFETS
Grant 6,404,269 - Voldman June 11, 2 | 2002-06-11 |
BiCMOS ESD circuit with subcollector/trench-isolated body mosfet for mixed signal analog/digital RF applications
App 20020066929 - Voldman, Steven H. | 2002-06-06 |
Method For Producing A Polysilicon Circuit Element
App 20020063291 - BROWN, JEFFREY S. ; et al. | 2002-05-30 |
Trench-defined silicon germanium ESD diode network
Grant 6,396,107 - Brennan , et al. May 28, 2 | 2002-05-28 |
Diffusion Resistor/capacitor (drc) Non-aligned Mosfet Structure
App 20020060343 - GAUTHIER, ROBERT J. ; et al. | 2002-05-23 |
Asymmetrical semiconductor device for ESD protection
App 20020056882 - Gauthier,, Robert J. JR. ; et al. | 2002-05-16 |
Thermal conductivity enhanced semiconductor structures and fabrication processes
Grant 6,387,742 - Gauthier, Jr. , et al. May 14, 2 | 2002-05-14 |
Gate overvoltage control networks
Grant 6,380,570 - Voldman April 30, 2 | 2002-04-30 |
SOI voltage dependent negative-saturation-resistance resistor ballasting element for ESD protection of receivers and driver circuitry
Grant 6,331,726 - Voldman December 18, 2 | 2001-12-18 |
Integrated high-performance decoupling capacitor and heat sink
App 20010050408 - Bernstein, Kerry ; et al. | 2001-12-13 |
Soi Voltage-tolerant Body-coupled Pass Transistor
App 20010043112 - VOLDMAN, STEVEN H | 2001-11-22 |
Process of forming a thick oxide field effect transistor
App 20010041393 - Hargrove, Michael J. ; et al. | 2001-11-15 |
MOSFET with lateral resistor ballasting
App 20010031552 - Gauthier, Robert J. JR. ; et al. | 2001-10-18 |
Thermal conductivity enhanced semiconductor structures and fabrication processes
App 20010029084 - Gauthier, Robert J. JR. ; et al. | 2001-10-11 |
Thermal conductivity enhanced semiconductor structures and fabrication processes
Grant 6,288,426 - Gauthier, Jr. , et al. September 11, 2 | 2001-09-11 |
Method for providing ESD protection for an integrated circuit
Grant 6,262,873 - Pequignot , et al. July 17, 2 | 2001-07-17 |
Method for forming transistors with raised source and drains and device formed thereby
Grant 6,255,178 - Brown , et al. July 3, 2 | 2001-07-03 |
Method and apparatus for providing electrostatic discharge protection
Grant 6,256,184 - Gauthier Jr. , et al. July 3, 2 | 2001-07-03 |
Integrated high-performance decoupling capacitor and heat sink
Grant 6,236,103 - Bernstein , et al. May 22, 2 | 2001-05-22 |
Method of forming a semiconductor diode with depleted polysilicon gate structure
Grant 6,232,163 - Voldman , et al. May 15, 2 | 2001-05-15 |
ESD protection structure and method
Grant 6,218,704 - Brown , et al. April 17, 2 | 2001-04-17 |
Support chips for buffer circuits
Grant 6,198,136 - Voldman , et al. March 6, 2 | 2001-03-06 |
Semiconductor structure having heterogeneous silicide regions and method for forming same
Grant 6,187,617 - Gauthier, Jr. , et al. February 13, 2 | 2001-02-13 |
Method and apparatus for providing ESD protection
Grant 6,157,530 - Pequignot , et al. December 5, 2 | 2000-12-05 |
Method for forming transistors with raised source and drains and device formed thereby
Grant 6,100,013 - Brown , et al. August 8, 2 | 2000-08-08 |
Method of making a depleted poly-silicon edged MOSFET structure
Grant 6,100,143 - Brown , et al. August 8, 2 | 2000-08-08 |
Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region
Grant 6,096,584 - Ellis-Monaghan , et al. August 1, 2 | 2000-08-01 |
Method and structure for increasing the threshold voltage of a corner device
Grant 6,097,069 - Brown , et al. August 1, 2 | 2000-08-01 |
Method of automated ESD protection level verification
Grant 6,086,627 - Bass, Jr. , et al. July 11, 2 | 2000-07-11 |
Switchable active clamp network
Grant 6,075,399 - Voldman , et al. June 13, 2 | 2000-06-13 |
Electrical contact to buried SOI structures
Grant 6,071,803 - Rutten , et al. June 6, 2 | 2000-06-06 |
Silicon-on-insulator body- and dual gate-coupled diode for electrostatic discharge (ESD) applications
Grant 6,034,397 - Voldman March 7, 2 | 2000-03-07 |
Depleted polysilicon circuit element and method for producing the same
Grant 6,034,388 - Brown , et al. March 7, 2 | 2000-03-07 |
Semiconductor diode with depleted polysilicon gate structure and method
Grant 6,015,993 - Voldman , et al. January 18, 2 | 2000-01-18 |
Silicon-on-insulator and CMOS-on-SOI double film structures
Grant 5,952,695 - Ellis-Monaghan , et al. September 14, 1 | 1999-09-14 |
Structure and process for buried diode formation in CMOS
Grant 5,939,767 - Brown , et al. August 17, 1 | 1999-08-17 |
Modified keeper half-latch receiver circuit
Grant 5,894,230 - Voldman April 13, 1 | 1999-04-13 |
Electrical contact to buried SOI structures
Grant 5,889,293 - Rutten , et al. March 30, 1 | 1999-03-30 |
Process for buried diode formation in CMOS
Grant 5,882,967 - Brown , et al. March 16, 1 | 1999-03-16 |
Dual thin oxide ESD network for nonvolatile memory applications
Grant 5,872,378 - Rose , et al. February 16, 1 | 1999-02-16 |
Magnetic head/silicon chip integration method
Grant 5,867,888 - Voldman , et al. February 9, 1 | 1999-02-09 |
Method and structure to reduce latch-up using edge implants
Grant 5,861,330 - Baker , et al. January 19, 1 | 1999-01-19 |
Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications
Grant 5,811,857 - Assaderaghi , et al. September 22, 1 | 1998-09-22 |
Decoupling capacitor network for off-state operation
Grant 5,789,964 - Voldman August 4, 1 | 1998-08-04 |
Method and apparatus for providing electrostatic discharge protection for an inductive coil of a magnetic transducer
Grant 5,777,829 - Voldman , et al. July 7, 1 | 1998-07-07 |
Three-dimensional monolithic electronic module having stacked planar arrays of integrated circuit chips
Grant 5,637,912 - Cockerill , et al. June 10, 1 | 1997-06-10 |
Semiconductor diode with silicide films and trench isolation
Grant 5,629,544 - Voldman , et al. May 13, 1 | 1997-05-13 |
Power sequence independent electrostatic discharge protection circuits
Grant 5,610,791 - Voldman March 11, 1 | 1997-03-11 |
Silicon chip with an integrated magnetoresistive head mounted on a slider
Grant 5,587,857 - Voldman , et al. December 24, 1 | 1996-12-24 |
Process for manufacturing a silicon chip with an integrated magnetoresistive head mounted on a slider
Grant 5,559,051 - Voldman , et al. September 24, 1 | 1996-09-24 |
Method of making double grid substrate plate DRAM cell array
Grant 5,521,115 - Park , et al. May 28, 1 | 1996-05-28 |
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