loadpatents
name:-0.099836111068726
name:-0.068583965301514
name:-0.0071861743927002
VO; NHAT D. Patent Filings

VO; NHAT D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for VO; NHAT D..The latest application filed is for "semiconductor device package with seal structure".

Company Profile
0.4.8
  • VO; NHAT D. - AUSTIN TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor Device Package With Seal Structure
App 20170081178 - SPEIGHT; THOMAS C. ;   et al.
2017-03-23
Tin-based Wirebond Structures
App 20140367859 - Carpenter; Burton J. ;   et al.
2014-12-18
Integrated circuit having pads and input/output (I/O) cells
Grant 7,808,117 - Vo , et al. October 5, 2
2010-10-05
Integrated Circuit Having Pads And Input/output (i/o) Cells
App 20070267755 - Vo; Nhat D. ;   et al.
2007-11-22
Integrated Circuit Having Pads And Input/output (i/o) Cells
App 20070267748 - Tran; Tu-Anh N. ;   et al.
2007-11-22
Solderable metal finish for integrated circuit package leads and method for forming
Grant 7,215,014 - Su , et al. May 8, 2
2007-05-08
Packaged semiconductor with coated leads and method therefore
Grant 7,105,383 - Vo , et al. September 12, 2
2006-09-12
Solderable metal finish for integrated circuit package leads and method for forming
App 20060022313 - Su; Peng ;   et al.
2006-02-02
Packaged semiconductor with coated leads and method therefore
App 20040041241 - Vo, Nhat D. ;   et al.
2004-03-04
Packaged integrated circuit and method therefor
Grant 6,617,524 - Vo September 9, 2
2003-09-09
Packaged Integrated Circuit And Method Therefor
App 20030106707 - Vo, Nhat D.
2003-06-12
Apparatus for connecting a semiconductor die to a substrate and method therefor
App 20020079595 - Carpenter, Burton J. ;   et al.
2002-06-27

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