Vitale; Steven A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vitale; Steven A..The latest application filed is for "interconnect structures for assembly of multi-layer semiconductor devices".

Company Profile

1.7.11

Vitale; Steven A. - Waltham MA
Vitale; Steven A. - Murphy TX US
Vitale, Steven A. - Staten Island NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor structures for assembly in multi-layer semiconductor devices including at least one semiconductor structure Grant 10,418,350 - Das , et al. Sept	2019-09-17
Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure Grant 10,079,224 - Das , et al. September 18, 2	2018-09-18
Interconnect structures for assembly of multi-layer semiconductor devices Grant 9,780,075 - Das , et al. October 3, 2	2017-10-03
Interconnect Structures for Assembly of Multi-Layer Semiconductor Devices App 20170200700 - Das; Rabindra N. ; et al.	2017-07-13
Semiconductor Structures For Assembly In Multi-Layer Semiconductor Devices Including At Least One Semiconductor Structure App 20170162507 - Das; Rabindra N. ; et al.	2017-06-08
Interconnect Structures For Assembly Of Semiconductor Structures Including At Least One Integrated Circuit Structure App 20170162550 - Das; Rabindra N. ; et al.	2017-06-08
Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device Grant 8,574,980 - Mehrad , et al. November 5, 2	2013-11-05
Solid-state Neutron Detector With Gadolinium Converter App 20130056641 - Vitale; Steven A. ; et al.	2013-03-07
Method Of Simultaneously Siliciding A Polysilicon Gate And Source/drain Of A Semiconductor Device, And Related Device App 20100176462 - Mehrad; Freidoon ; et al.	2010-07-15
Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device Grant 7,727,842 - Mehrad , et al. June 1, 2	2010-06-01
Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, and Related Device App 20090321846 - Mehrad; Freidoon ; et al.	2009-12-31
Method Of Forming Fully Silicided Nmos And Pmos Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, And Related Device App 20090057776 - Mehrad; Freidoon ; et al.	2009-03-05
Method Of Simultaneously Siliciding A Polysilicon Gate And Source/drain Of A Semiconductor Device, And Related Device App 20080265344 - Mehrad; Freidoon ; et al.	2008-10-30
Method to obtain fully silicided gate electrodes Grant 7,244,642 - Vitale , et al. July 17, 2	2007-07-17
Method to obtain fully silicided gate electrodes App 20070066007 - Vitale; Steven A. ; et al.	2007-03-22
Underground vault security system App 20040168620 - Vitale, Steven A. ; et al.	2004-09-02

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