Viswanath; Manikandan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Viswanath; Manikandan.The latest application filed is for "apportioning synthesis effort for better timing closure".

Company Profile

0.10.10

Viswanath; Manikandan - South Burlington VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apportioning synthesis effort for better timing closure Grant 9,298,872 - Nam , et al. March 29, 2	2016-03-29
Apportioning Synthesis Effort For Better Timing Closure App 20150234971 - Nam; Gi-Joon ; et al.	2015-08-20
Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics Grant 8,862,417 - Chu , et al. October 14, 2	2014-10-14
Soft pin insertion during physical design Grant 8,782,589 - Viswanath , et al. July 15, 2	2014-07-15
Soft Pin Insertion During Physical Design App 20140189630 - Viswanath; Manikandan ; et al.	2014-07-03
Optimizing timing critical paths by modulating systemic process variation Grant 8,726,210 - Chu , et al. May 13, 2	2014-05-13
Spare cell insertion based on reachable state analysis Grant 8,661,391 - Viswanath , et al. February 25, 2	2014-02-25
Optimizing Timing Critical Paths By Modulating Systemic Process Variation App 20130239078 - CHU; Albert M. ; et al.	2013-09-12
Systems And Methods For Determining Adjustable Wafer Acceptance Criteria Based On Chip Characteristics App 20120310574 - CHU; Albert M. ; et al.	2012-12-06
Design System And Method That, During Timing Analysis, Compensates For Regional Timing Variations App 20110107291 - Barwin; John E. ; et al.	2011-05-05
Design structure for performing iterative synthesis of an integrated circuit design to attain power closure Grant 7,886,253 - Charlebois , et al. February 8, 2	2011-02-08
Power gating logic cones Grant 7,873,923 - Charlebois , et al. January 18, 2	2011-01-18
Power Gating Logic Cones App 20090222772 - Charlebois; Steven E ; et al.	2009-09-03
Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints Grant 7,539,968 - Charlebois , et al. May 26, 2	2009-05-26
Structure For Performing Iterative Synthesis Of An Integrated Circuit Design To Attain Power Closure App 20090100398 - Charlebois; Steven E. ; et al.	2009-04-16
Iterative Synthesis Of An Integrated Circuit Design For Attaining Power Closure While Maintaining Existing Design Constraints App 20080307383 - Charlebois; Steven E. ; et al.	2008-12-11
Method To Identify And Generate Critical Timing Path Test Vectors App 20080263489 - Canada; Miles G. ; et al.	2008-10-23

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.