Vinh; James
Patent Applications and Registrations
Patent applications and USPTO patent grants for Vinh; James.The latest application filed is for "word line late kill in scheduler".
- Vinh; James - San Jose CA US
| Patent | Date |
|---|---|
| Selectable multi-way comparator Grant 8,787,058 - Venkataramanan , et al. July 22, 2 | 2014-07-22 |
| Method and apparatus for prioritizing processor scheduler queue operations Grant 8,656,401 - Venkataramanan , et al. February 18, 2 | 2014-02-18 |
| Low power content-addressable memory and method Grant 8,570,783 - Venkataramanan , et al. October 29, 2 | 2013-10-29 |
| CMOS circuit with dynamic parasitic net pulldown circuit Grant 8,461,877 - Viau , et al. June 11, 2 | 2013-06-11 |
| Selectable Multi-way Comparator App 20130039109 - Venkataramanan; Ganesh ; et al. | 2013-02-14 |
| Word Line Late Kill In Scheduler App 20130042089 - Vinh; James ; et al. | 2013-02-14 |
| Cmos Circuit With Dynamic Parasitic Net Pulldown Circuit App 20130002303 - Viau; Kyle S. ; et al. | 2013-01-03 |
| Method And Apparatus For Prioritizing Processor Scheduler Queue Operations App 20120291037 - Venkataramanan; Ganesh ; et al. | 2012-11-15 |
| Memory Built-in Self Test Scheme For Content Addressable Memory Array App 20120140541 - Viau; Kyle S. ; et al. | 2012-06-07 |
| Multi-issue Unified Integer Scheduler App 20120144393 - Vinh; James ; et al. | 2012-06-07 |
| Low Power Content-addressable Memory And Method App 20120110256 - Venkataramanan; Ganesh ; et al. | 2012-05-03 |
| Method and apparatus for reduction of noise sensitivity in dynamic logic circuits Grant 6,603,333 - Vinh , et al. August 5, 2 | 2003-08-05 |
| Method and apparatus for a family of self clocked dynamic circuits Grant 6,407,585 - Vinh June 18, 2 | 2002-06-18 |
| Method and apparatus for reduction of noise sensitivity in dynamic logic circuits App 20020067188 - Vinh, James ; et al. | 2002-06-06 |
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