| Patent | Date |
|---|
Device With Two Superposed Electrostatic Control Gate Levels
App 20220292384 - BERTRAND; Benoit ; et al. | 2022-09-15 |
Device Comprising Electrostatic Control Gates Distributed On Two Opposite Faces Of A Semiconductor Portion
App 20220271151 - BEDECARRATS; Thomas ; et al. | 2022-08-25 |
Method for producing an electronic component with double quantum dots
Grant 11,398,593 - Barraud , et al. July 26, 2 | 2022-07-26 |
Quantum Device And Method For Producing The Same
App 20220173229 - POSSEME; Nicolas ; et al. | 2022-06-02 |
Method Of Making A Quantum Device
App 20220172093 - POSSEME; Nicolas ; et al. | 2022-06-02 |
Quantum device with spin qubits coupled in modulatable manner
Grant 11,329,145 - Hutin , et al. May 10, 2 | 2022-05-10 |
Method for controlling a spin qubit quantum device
Grant 11,321,626 - Bourdet , et al. May 3, 2 | 2022-05-03 |
Integrated Structure With Bifunctional Routing And Assembly Comprising Such A Structure
App 20220093500 - THOMAS; Candice ; et al. | 2022-03-24 |
Chip With Bifunctional Routing And Associated Method Of Manufacturing
App 20220093501 - THOMAS; Candice ; et al. | 2022-03-24 |
Process for producing FET transistors
Grant 11,264,479 - Grenouillet , et al. March 1, 2 | 2022-03-01 |
Method of manufacturing an electronic component including multiple quantum dots
Grant 11,088,259 - Hutin , et al. August 10, 2 | 2021-08-10 |
Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer
Grant 11,011,425 - Batude , et al. May 18, 2 | 2021-05-18 |
Internal via with improved contact for upper semi-conductor layer of a 3D circuit
Grant 10,930,562 - Fenouillet-Beranger , et al. February 23, 2 | 2021-02-23 |
Electronic component with multiple quantum islands
Grant 10,903,349 - Hutin , et al. January 26, 2 | 2021-01-26 |
Method For Producing An Electronic Component With Double Quantum Dots
App 20200343435 - BARRAUD; Sylvain ; et al. | 2020-10-29 |
Method For Controlling A Spin Qubit Quantum Device
App 20200226486 - BOURDET; Leo ; et al. | 2020-07-16 |
Quantum device comprising FET transistors and qubits co-integrated on the same substrate
Grant 10,679,139 - Hutin , et al. | 2020-06-09 |
3D circuit transistors with flipped gate
Grant 10,651,202 - Andrieu , et al. | 2020-05-12 |
Quantum device with spin qubits
Grant 10,607,993 - Hutin , et al. | 2020-03-31 |
Production Of A 3d Circuit With Upper Level Transistor Provided With A Gate Dielectric Derived From A Substrate Transfer
App 20200035561 - BATUDE; Perrine ; et al. | 2020-01-30 |
Method Of Manufacturing An Electronic Component Including Quantum Dots
App 20190371926 - HUTIN; Louis ; et al. | 2019-12-05 |
Method Of Manufacturing An Electronic Component Including Multiple Quantum Dots
App 20190371908 - HUTIN; Louis ; et al. | 2019-12-05 |
Internal Via With Improved Contact For Upper Semi-conductor Layer Of A 3d Circuit
App 20190371671 - FENOUILLET-BERANGER; Claire ; et al. | 2019-12-05 |
Method of manufacturing a LED matrix display device
Grant 10,468,436 - Robin , et al. No | 2019-11-05 |
Quantum Device Comprising Fet Transistors And Qubits Co-integrated On The Same Substrate
App 20190266509 - HUTIN; Louis ; et al. | 2019-08-29 |
Integrated circuit having a plurality of active layers and method of fabricating the same
Grant 10,319,628 - Deprat , et al. | 2019-06-11 |
3d Circuit Transistors With Flipped Gate
App 20190157300 - ANDRIEU; Francois ; et al. | 2019-05-23 |
Quantum Device With Spin Qubits Coupled In Modulatable Manner
App 20190123183 - HUTIN; Louis ; et al. | 2019-04-25 |
Quantum Device With Spin Qubits
App 20180331108 - Hutin; Louis ; et al. | 2018-11-15 |
Method Of Manufacturing A Led Matrix Display Device
App 20180301479 - Robin; Ivan-Christophe ; et al. | 2018-10-18 |
Method of making a transistor
Grant 9,978,602 - Niebojewski , et al. May 22, 2 | 2018-05-22 |
Integrated Circuit Having A Plurality Of Active Layers And Method Of Fabricating The Same
App 20180090366 - DEPRAT; Fabien ; et al. | 2018-03-29 |
Single-electron transistor and its fabrication method
Grant 9,911,841 - Barraud , et al. March 6, 2 | 2018-03-06 |
Method for making a transistor in a stack of superimposed semiconductor layers
Grant 9,876,121 - Barraud , et al. January 23, 2 | 2018-01-23 |
Isolation regions for SOI devices
Grant 9,768,055 - Liu , et al. September 19, 2 | 2017-09-19 |
Method for making a three dimensional integrated electronic circuit
Grant 9,721,850 - Previtali , et al. August 1, 2 | 2017-08-01 |
Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location
Grant 9,711,567 - Grenouillet , et al. July 18, 2 | 2017-07-18 |
Method for manufacturing a fin MOS transistor
Grant 9,673,329 - Morand , et al. June 6, 2 | 2017-06-06 |
CMOS in situ doped flow with independently tunable spacer thickness
Grant 9,634,103 - Vinet , et al. April 25, 2 | 2017-04-25 |
Low leakage dual STI integrated circuit including FDSOI transistors
Grant 9,601,511 - Vinet , et al. March 21, 2 | 2017-03-21 |
Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same
Grant 9,570,465 - Vinet , et al. February 14, 2 | 2017-02-14 |
Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on hydrogen chloride
Grant 9,570,340 - Grenouillet , et al. February 14, 2 | 2017-02-14 |
Dual shallow trench isolation liner for preventing electrical shorts
Grant 9,502,292 - Doris , et al. November 22, 2 | 2016-11-22 |
Method For Fabricating An Integrated Circuit Co-integrating A Fet Transistor And An Oxram Memory Point
App 20160300884 - GRENOUILLET; Laurent ; et al. | 2016-10-13 |
Method For Making A Transistor In A Stack Of Superimposed Semiconductor Layers
App 20160276494 - BARRAUD; Sylvain ; et al. | 2016-09-22 |
Single-electron Transistor And Its Fabrication Method
App 20160268406 - BARRAUD; Sylvain ; et al. | 2016-09-15 |
Matching of transistors
Grant 9,443,933 - Allibert , et al. September 13, 2 | 2016-09-13 |
Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
Grant 9,437,474 - Grenouillet , et al. September 6, 2 | 2016-09-06 |
Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
Grant 9,437,475 - Vinet , et al. September 6, 2 | 2016-09-06 |
Method for producing a silicon-germanium film with variable germanium content
Grant 9,425,051 - Vinet , et al. August 23, 2 | 2016-08-23 |
Method For Making A Three Dimensional Integrated Electronic Circuit
App 20160211184 - Previtali; Bernard ; et al. | 2016-07-21 |
Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation trenches partially formed under an active region
Grant 9,396,984 - Vinet , et al. July 19, 2 | 2016-07-19 |
Method for forming doped areas under transistor spacers
Grant 9,379,213 - Batude , et al. June 28, 2 | 2016-06-28 |
Defective P-N junction for backgated fully depleted silicon on insulator mosfet
Grant 9,373,507 - Cheng , et al. June 21, 2 | 2016-06-21 |
Uniaxially-strained Fd-soi Finfet
App 20160133692 - Morin; Pierre ; et al. | 2016-05-12 |
Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same
Grant 9,337,350 - Posseme , et al. May 10, 2 | 2016-05-10 |
Method For Manufacturing A Fin Mos Transistor
App 20160087092 - Morand; Yves ; et al. | 2016-03-24 |
Dual channel hybrid semiconductor-on-insulator semiconductor devices
Grant 9,293,474 - Cheng , et al. March 22, 2 | 2016-03-22 |
Method Of Making A Transistor
App 20160042955 - NIEBOJEWSKI; Heimanu ; et al. | 2016-02-11 |
Cmos In Situ Doped Flow With Independently Tunable Spacer Thickness
App 20160035843 - VINET; Maud ; et al. | 2016-02-04 |
Uniaxially-strained Fd-soi Finfet
App 20160035820 - Morin; Pierre ; et al. | 2016-02-04 |
Uniaxially-strained FD-SOI finFET
Grant 9,252,208 - Morin , et al. February 2, 2 | 2016-02-02 |
Dual shallow trench isolation liner for preventing electrical shorts
Grant 9,252,052 - Doris , et al. February 2, 2 | 2016-02-02 |
Low Leakage Dual Sti Integrated Circuit Including Fdsoi Transistors
App 20160013206 - VINET; Maud ; et al. | 2016-01-14 |
Dual Sti Integrated Circuit Including Fdsoi Transistors And Method For Manufacturing The Same
App 20160013205 - VINET; Maud ; et al. | 2016-01-14 |
Dual Shallow Trench Isolation Liner For Preventing Electrical Shorts
App 20160013096 - Doris; Bruce B. ; et al. | 2016-01-14 |
Method for manufacturing a fin MOS transistor
Grant 9,236,478 - Morand , et al. January 12, 2 | 2016-01-12 |
Method for treating the surface of a silicon substrate
Grant 9,231,062 - Le Tiec , et al. January 5, 2 | 2016-01-05 |
Method Of Producing A Microelectronic Device In A Monocrystalline Semiconductor Substrate With Isolation Trenches Partially Formed Under An Active Region
App 20150340275 - VINET; Maud ; et al. | 2015-11-26 |
Dual shallow trench isolation liner for preventing electrical shorts
Grant 9,171,757 - Doris , et al. October 27, 2 | 2015-10-27 |
Method For Fabricating Microelectronic Devices With Isolation Trenches Partially Formed Under Active Regions
App 20150294904 - Vinet; Maud ; et al. | 2015-10-15 |
Process For Producing Fet Transistors
App 20150295066 - Grenouillet; Laurent ; et al. | 2015-10-15 |
Method For Fabricating Microelectronic Devices With Isolation Trenches Partially Formed Under Active Regions
App 20150294903 - Grenouillet; Laurent ; et al. | 2015-10-15 |
Dual Channel Hybrid Semiconductor-on-insulator Semiconductor Devices
App 20150279861 - Cheng; Kangguo ; et al. | 2015-10-01 |
Transistor with coupled gate and ground plane
Grant 9,136,366 - Giraud , et al. September 15, 2 | 2015-09-15 |
Field effect device provided with a thinned counter-electrode and method for fabricating
Grant 9,123,814 - Grenouillet , et al. September 1, 2 | 2015-09-01 |
Transistor with counter-electrode connection amalgamated with the source/drain contact
Grant 9,112,014 - Vinet , et al. August 18, 2 | 2015-08-18 |
Contact isolation scheme for thin buried oxide substrate devices
Grant 9,105,691 - Cheng , et al. August 11, 2 | 2015-08-11 |
Matching Of Transistors
App 20150221723 - Allibert; Frederic ; et al. | 2015-08-06 |
Method Of Etching A Crystalline Semiconductor Material By Ion Implantation And Then Chemical Etching Based On Hydrogen Chloride
App 20150214099 - Grenouillet; Laurent ; et al. | 2015-07-30 |
Method to prepare semi-conductor device comprising a selective etching of a silicium--germanium layer
Grant 9,076,732 - Le Tiec , et al. July 7, 2 | 2015-07-07 |
Method for producing a field effect transistor with implantation through the spacers
Grant 9,070,709 - Posseme , et al. June 30, 2 | 2015-06-30 |
Defective P-n Junction For Backgated Fully Depleted Silicon On Insulator Mosfet
App 20150179453 - CHENG; KANGGUO ; et al. | 2015-06-25 |
Dual channel hybrid semiconductor-on-insulator semiconductor devices
Grant 9,059,041 - Cheng , et al. June 16, 2 | 2015-06-16 |
Field effect transistor with offset counter-electrode contact
Grant 8,994,142 - Vinet , et al. March 31, 2 | 2015-03-31 |
Microelectronic device with isolation trenches extending under an active area
Grant 8,987,854 - Vinet , et al. March 24, 2 | 2015-03-24 |
Method of making a transistor
Grant 8,980,702 - Niebojewski , et al. March 17, 2 | 2015-03-17 |
Method for producing a transistor structure with superimposed nanowires and with a surrounding gate
Grant 8,969,148 - Vinet , et al. March 3, 2 | 2015-03-03 |
Defective P-N junction for backgated fully depleted silicon on insulator MOSFET
Grant 8,969,966 - Cheng , et al. March 3, 2 | 2015-03-03 |
Method For Separation Between An Active Zone Of A Substrate And Its Back Face Or A Portion Of Its Back Face
App 20150056734 - Grenouillet; Laurent ; et al. | 2015-02-26 |
Method of making a semiconductor layer having at least two different thicknesses
Grant 8,962,399 - Vinet , et al. February 24, 2 | 2015-02-24 |
Method For Forming Doped Areas Under Transistor Spacers
App 20150044841 - BATUDE; Perrine ; et al. | 2015-02-12 |
Dual Channel Hybrid Semiconductor-on-insulator Semiconductor Devices
App 20150008520 - Cheng; Kangguo ; et al. | 2015-01-08 |
Method Of Making A Semiconductor Layer Having At Least Two Different Thicknesses
App 20140370666 - VINET; Maud ; et al. | 2014-12-18 |
Method Of Making A Transitor
App 20140370668 - NIEBOJEWSKI; Heimanu ; et al. | 2014-12-18 |
Method for producing a silicon-germanium film with variable germanium content
App 20140349460 - VINET; Maud ; et al. | 2014-11-27 |
UTBB CMOS imager having a diode junction in a photosensitive area thereof
Grant 8,890,219 - Grenouillet , et al. November 18, 2 | 2014-11-18 |
Method Of Making A Transitor
App 20140335663 - NIEBOJEWSKI; Heimanu ; et al. | 2014-11-13 |
Method for producing a field effect transistor with a SiGe channel by ion implantation
Grant 8,877,618 - Grenouillet , et al. November 4, 2 | 2014-11-04 |
Defective P-n Junction For Backgated Fully Depleted Silicon On Insulator Mosfet
App 20140312461 - Cheng; Kangguo ; et al. | 2014-10-23 |
Contact Isolation Scheme For Thin Buried Oxide Substrate Devices
App 20140302661 - Cheng; Kangguo ; et al. | 2014-10-09 |
Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit
Grant 8,853,785 - Augendre , et al. October 7, 2 | 2014-10-07 |
Method For Manufacturing A Fin Mos Transistor
App 20140246723 - MORAND; YVES ; et al. | 2014-09-04 |
Transistor with coupled gate and ground plane
App 20140231916 - Giraud; Bastien ; et al. | 2014-08-21 |
Method of producing insulation trenches in a semiconductor on insulator substrate
Grant 8,735,259 - Le Tiec , et al. May 27, 2 | 2014-05-27 |
Light-emitting device with head-to-tail P-type and N-type transistors
Grant 8,729,577 - Grenouillet , et al. May 20, 2 | 2014-05-20 |
Method for fabricating a field effect device with weak junction capacitance
Grant 8,722,499 - Vinet , et al. May 13, 2 | 2014-05-13 |
METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH A SiGe CHANNEL BY ION IMPLANTATION
App 20140127871 - GRENOUILLET; Laurent ; et al. | 2014-05-08 |
Dual shallow trench isolation liner for preventing electrical shorts
Grant 8,703,550 - Doris , et al. April 22, 2 | 2014-04-22 |
Dual Shallow Trench Isolation Liner For Preventing Electrical Shorts
App 20140099773 - Doris; Bruce B. ; et al. | 2014-04-10 |
Dual Shallow Trench Isolation Liner For Preventing Electrical Shorts
App 20140084372 - Doris; Bruce B. ; et al. | 2014-03-27 |
Method For Producing A Field Effect Transistor With Implantation Through The Spacers
App 20140087524 - Posseme; Nicolas ; et al. | 2014-03-27 |
Microelectronic Device With Isolation Trenches Extending Under An Active Area
App 20140061798 - VINET; Maud ; et al. | 2014-03-06 |
Electronic Device Including Shallow Trench Isolation (sti) Regions With Bottom Oxide Liner And Upper Nitride Liner And Related Methods
App 20140054699 - LIU; QING ; et al. | 2014-02-27 |
Dual Shallow Trench Isolation Liner For Preventing Electrical Shorts
App 20130334651 - Doris; Bruce B. ; et al. | 2013-12-19 |
Field effect device provided with a localized dopant diffusion barrier area and fabrication method
Grant 8,603,872 - Grenouillet , et al. December 10, 2 | 2013-12-10 |
Method For Treating The Surface Of A Silicon Substrate
App 20130309449 - Le Tiec; Yannick ; et al. | 2013-11-21 |
Method For Producing A Transistor Structure With Superimposed Nanowires And With A Surrounding Gate
App 20130302955 - VINET; MAUD ; et al. | 2013-11-14 |
Transistor With Counter-electrode Connection Amalgamated With The Source/drain Contact
App 20130193494 - Vinet; Maud ; et al. | 2013-08-01 |
Method Of Producing Insulation Trenches In A Semiconductor On Insulator Substrate
App 20130189825 - LE TIEC; Yannick ; et al. | 2013-07-25 |
Transistor And Method Of Fabrication
App 20130161746 - POSSEME; Nicolas ; et al. | 2013-06-27 |
Utbb Cmos Imager
App 20130113066 - GRENOUILLET; Laurent ; et al. | 2013-05-09 |
Light-emitting Device With Head-to-tail P-type And N-type Transistors
App 20130113004 - GRENOUILLET; Laurent ; et al. | 2013-05-09 |
Method To Prepare Semi-conductor Device Comprising A Selective Etching Of A Silicium-germanium Layer
App 20130109191 - LE TIEC; Yannick ; et al. | 2013-05-02 |
Method for making asymmetric double-gate transistors
Grant 8,399,316 - Vinet , et al. March 19, 2 | 2013-03-19 |
Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate
Grant 8,324,057 - Vinet , et al. December 4, 2 | 2012-12-04 |
Field Effect Transistor With Offset Counter-electrode Contact
App 20120256262 - VINET; Maud ; et al. | 2012-10-11 |
Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate
Grant 8,232,168 - Vinet , et al. July 31, 2 | 2012-07-31 |
Field Effect Device Provided With A Thinned Counter-electrode And Method For Fabricating
App 20120187488 - GRENOUILLET; Laurent ; et al. | 2012-07-26 |
Method For Fabricating A Field Effect Device With Weak Junction Capacitance
App 20120190214 - Vinet; Maud ; et al. | 2012-07-26 |
Field Effect Device Provided With A Localized Dopant Diffusion Barrier Area And Fabrication Method
App 20120187489 - GRENOUILLET; Laurent ; et al. | 2012-07-26 |
Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT
Grant 8,183,630 - Batude , et al. May 22, 2 | 2012-05-22 |
Memory cell provided with dual-gate transistors, with independent asymmetric gates
Grant 8,116,118 - Thomas , et al. February 14, 2 | 2012-02-14 |
Device for measuring metal/semiconductor contact resistivity
Grant 8,115,503 - Vinet February 14, 2 | 2012-02-14 |
Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate
Grant 8,105,906 - Vinet , et al. January 31, 2 | 2012-01-31 |
Method for making a transistor with metallic source and drain
Grant 8,021,934 - Vinet , et al. September 20, 2 | 2011-09-20 |
Method for producing a transistor with metallic source and drain
Grant 8,021,986 - Previtali , et al. September 20, 2 | 2011-09-20 |
SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable
Grant 8,013,399 - Thomas , et al. September 6, 2 | 2011-09-06 |
Strained-channel transistor device
Grant 7,973,350 - Collonge , et al. July 5, 2 | 2011-07-05 |
Microelectronic device provided with transistors coated with a piezoelectric layer
Grant 7,968,945 - Lolivier , et al. June 28, 2 | 2011-06-28 |
Integrated Circuit With Electrostatically Coupled Mos Transistors And Method For Producing Such An Integrated Circuit
App 20110147849 - AUGENDRE; Emmanuel ; et al. | 2011-06-23 |
Method For Producing A Transistor With Metallic Source And Drain
App 20110003443 - Previtali; Bernard ; et al. | 2011-01-06 |
Method For Fabricating Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate
App 20100320541 - Vinet; Maud ; et al. | 2010-12-23 |
Method For Making Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate
App 20100317167 - Vinet; Maud ; et al. | 2010-12-16 |
Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor
Grant 7,829,916 - Morand , et al. November 9, 2 | 2010-11-09 |
Suspended-gate MOS transistor with non-volatile operation
Grant 7,812,410 - Collonge , et al. October 12, 2 | 2010-10-12 |
Non-volatile SRAM memory cell equipped with mobile gate transistors and piezoelectric operation
Grant 7,768,821 - Thomas , et al. August 3, 2 | 2010-08-03 |
Method For Making Asymmetric Double-gate Transistors
App 20100178743 - Vinet; Maud ; et al. | 2010-07-15 |
Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals localised with precision
Grant 7,713,850 - Vinet , et al. May 11, 2 | 2010-05-11 |
Method For Fabricating Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate
App 20100096700 - Vinet; Maud ; et al. | 2010-04-22 |
Method of producing a transistor
Grant 7,678,635 - Clavelier , et al. March 16, 2 | 2010-03-16 |
Sram Memory Cell Having Transistors Integrated At Several Levels And The Threshold Voltage Vt Of Which Is Dynamically Adjustable
App 20090294861 - THOMAS; Olivier ; et al. | 2009-12-03 |
Circuit With Transistors Integrated In Three Dimensions And Having A Dynamically Adjustable Threshold Voltage Vt
App 20090294822 - Batude; Perrine ; et al. | 2009-12-03 |
Method For Making A Transistor With Metallic Source And Drain
App 20090286363 - VINET; Maud ; et al. | 2009-11-19 |
Thin layer element and associated fabrication process
Grant 7,579,226 - Barbe , et al. August 25, 2 | 2009-08-25 |
Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor
App 20090127584 - Morand; Yves ; et al. | 2009-05-21 |
Anchoring, by lateral oxidizing, of patterns of a thin film to prevent the dewetting phenomenon
Grant 7,510,919 - Barbe , et al. March 31, 2 | 2009-03-31 |
Method For Making A Transistor With Self-aligned Double Gates By Reducing Gate Patterns
App 20090079004 - LICITRA; Christophe ; et al. | 2009-03-26 |
Manufacturing process for a transistor made of thin layers
Grant 7,491,644 - Vinet , et al. February 17, 2 | 2009-02-17 |
Suspended-gate Mos Transistor With Non-volatile Operation
App 20090014769 - Collonge; Michael ; et al. | 2009-01-15 |
Non-volatile Sram Memory Cell Equipped With Mobile Gate Transistors And Piezoelectric Operation
App 20090016095 - Thomas; Olivier ; et al. | 2009-01-15 |
Method for insulating patterns formed in a thin film of oxidizable semi-conducting material
Grant 7,473,588 - Vinet , et al. January 6, 2 | 2009-01-06 |
Device For Measuring Metal/semiconductor Contact Resistivity
App 20080297180 - VINET; Maud | 2008-12-04 |
Microelectronic Device Provided with Transistors Coated with a Piezoelectric Layer
App 20080290384 - Lolivier; Jerome ; et al. | 2008-11-27 |
Strained-channel transistor device
App 20080283877 - Collonge; Michael ; et al. | 2008-11-20 |
Method for forming patterns aligned on either side of a thin film
Grant 7,425,509 - Vinet , et al. September 16, 2 | 2008-09-16 |
Method Of Producing A Transistor
App 20080200001 - CLAVELIER; Laurent ; et al. | 2008-08-21 |
Memory cell provided with dual-gate transistors, with independent asymmetric gates
App 20080175039 - Thomas; Olivier ; et al. | 2008-07-24 |
Method for producing a component comprising at least one germanium-based element and component obtained by such a method
Grant 7,361,592 - Morand , et al. April 22, 2 | 2008-04-22 |
Manufacturing process for a transistor made of thin layers
App 20070173064 - Vinet; Maud ; et al. | 2007-07-26 |
Method for producing a component comprising at least one germanium-based element and component obtained by such a method
App 20060276052 - Morand; Yves ; et al. | 2006-12-07 |
Method for forming patterns aligned on either side of a thin film
App 20060148256 - Vinet; Maud ; et al. | 2006-07-06 |
Method for insulating patterns formed in a thin film of oxidizable semi-conducting material
App 20060121653 - Vinet; Maud ; et al. | 2006-06-08 |
Thin layer element and associated fabrication process
App 20060060846 - Barbe; Jean-Charles ; et al. | 2006-03-23 |
Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals localised with precision
App 20060019459 - Vinet; Maud ; et al. | 2006-01-26 |
Anchoring, by lateral oxidizing, of patterns of a thin film to prevent the dewetting phenomenon
App 20060014333 - Barbe; Jean-Charles ; et al. | 2006-01-19 |
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