Villarrubia; Paul G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Villarrubia; Paul G..The latest application filed is for "automated design closure with abutted hierarchy".

Company Profile

12.41.37

Villarrubia; Paul G. - Austin TX
Villarrubia; Paul G - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory element graph-based placement in integrated circuit design Grant 11,080,443 - Kim , et al. August 3, 2	2021-08-03
Automated design closure with abutted hierarchy Grant 11,080,456 - Kazda , et al. August 3, 2	2021-08-03
Multi-cycle latch tree synthesis Grant 11,074,379 - Reddy , et al. July 27, 2	2021-07-27
Automated Design Closure With Abutted Hierarchy App 20210165856 - Kazda; Michael ; et al.	2021-06-03
Hierarchy-driven logical and physical synthesis co-optimization Grant 10,891,411 - Nam , et al. January 12, 2	2021-01-12
Propagating constants of structured soft blocks while preserving the relative placement structure Grant 10,803,224 - Shah , et al. October 13, 2	2020-10-13
Multi-cycle Latch Tree Synthesis App 20200311221 - Reddy; Lakshmi N. ; et al.	2020-10-01
Model-based refinement of the placement process in integrated circuit generation Grant 10,762,271 - Kim , et al. Sep	2020-09-01
Large cluster persistence during placement optimization of integrated circuit designs Grant 10,685,160 - Kim , et al.	2020-06-16
Hierarchy-driven Logical And Physical Synthesis Co-optimization App 20200175122 - Nam; Gi-Joon ; et al.	2020-06-04
Propagating Constants Of Structured Soft Blocks While Preserving The Relative Placement Structure App 20200159882 - Shah; Salim ; et al.	2020-05-21
Enhancing stability of half perimeter wire length (HPWL)-driven analytical placement Grant 10,635,773 - Kim , et al.	2020-04-28
Enhancing Stability Of Half Perimeter Wire Length (hpwl)-driven Analytical Placement App 20200125690 - Kim; Myung-Chul ; et al.	2020-04-23
Memory Element Graph-based Placement In Integrated Circuit Design App 20200125779 - Kim; Myung-Chul ; et al.	2020-04-23
Model-based Refinement Of The Placement Process In Integrated Circuit Generation App 20200104453 - Kim; Myung-Chul ; et al.	2020-04-02
Memory element graph-based placement in integrated circuit design Grant 10,558,775 - Kim , et al. Feb	2020-02-11
Integer Arithmetic Method For Wire Length Minimization In Global Placement With Convolution Based Density Penalty Computation App 20200034507 - Lvov; Alexey Y. ; et al.	2020-01-30
Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computation Grant 10,528,695 - Lvov , et al. J	2020-01-07
Memory Element Graph-based Placement In Integrated Circuit Design App 20190188352 - Kim; Myung-Chul ; et al.	2019-06-20
Large Cluster Persistence During Placement Optimization Of Integrated Circuit Designs App 20190026418 - Kim; Myung-Chul ; et al.	2019-01-24
Large cluster persistence during placement optimization of integrated circuit designs Grant 10,140,409 - Kim , et al. Nov	2018-11-27
Timing adjustments across transparent latches to facilitate power reduction Grant 9,754,062 - Kalafala , et al. September 5, 2	2017-09-05
Large Cluster Persistence During Placement Optimization Of Integrated Circuit Designs App 20170220722 - KIM; MYUNG-CHUL ; et al.	2017-08-03
Timing Adjustments Across Transparent Latches To Facilitate Power Reduction App 20170132347 - Kalafala; Kerim ; et al.	2017-05-11
Element placement in circuit design based on preferred location Grant 9,524,363 - Alpert , et al. December 20, 2	2016-12-20
Large cluster persistence during placement optimization of integrated circuit designs Grant 9,495,501 - Kim , et al. November 15, 2	2016-11-15
Multi power synthesis in digital circuit design Grant 9,483,596 - Badar , et al. November 1, 2	2016-11-01
Boundary latch and logic placement to satisfy timing constraints Grant 9,098,669 - Alpert , et al. August 4, 2	2015-08-04
Boundary Latch And Logic Placement To Satisfy Timing Constraints App 20150199465 - Alpert; Charles J. ; et al.	2015-07-16
Structured placement of latches/flip-flops to minimize clock power in high-performance designs Grant 8,954,912 - Alpert , et al. February 10, 2	2015-02-10
Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit Grant 8,954,915 - Chan , et al. February 10, 2	2015-02-10
Scheduling for parallel processing of regionally-constrained placement problem Grant 8,930,867 - Nam , et al. January 6, 2	2015-01-06
Structured Placement Of Hierarchical Soft Blocks During Physical Synthesis Of An Integrated Circuit App 20140359546 - Chan; Yiu-Hing ; et al.	2014-12-04
Routing centric design closure Grant 8,826,215 - Alpert , et al. September 2, 2	2014-09-02
Facilitating the design of a clock grid in an integrated circuit Grant 8,799,846 - Berry , et al. August 5, 2	2014-08-05
Post-placement cell shifting Grant 8,782,584 - Alpert , et al. July 15, 2	2014-07-15
Structured Placement Of Latches/flip-flops To Minimize Clock Power In High-performance Designs App 20140149957 - Alpert; Charles J. ; et al.	2014-05-29
Scheduling for Parallel Processing of Regionally-Constrained Placement Problem App 20140033154 - Nam; Gi-Joon ; et al.	2014-01-30
Post-placement Cell Shifting App 20130346938 - Alpert; Charles J ; et al.	2013-12-26
Element Placement In Circuit Design Based On Preferred Location App 20130326455 - Alpert; Charles J. ; et al.	2013-12-05
Scheduling for parallel processing of regionally-constrained placement problem Grant 8,578,315 - Nam , et al. November 5, 2	2013-11-05
Partitioning for hardware-accelerated functional verification Grant 8,555,221 - Moffitt , et al. October 8, 2	2013-10-08
Post-placement cell shifting Grant 8,495,534 - Alpert , et al. July 23, 2	2013-07-23
Buffer-aware routing in integrated circuit design Grant 8,370,782 - Alpert , et al. February 5, 2	2013-02-05
Detailed routability by cell placement Grant 8,347,257 - Alpert , et al. January 1, 2	2013-01-01
Partitioning For Hardware-accelerated Functional Verification App 20120317527 - Moffitt; Michael D. ; et al.	2012-12-13
Partitioning for hardware-accelerated functional verification Grant 8,327,304 - Moffitt , et al. December 4, 2	2012-12-04
Whitespace Creation And Preservation In Circuit Design App 20120297355 - Alpert; Charles Jay ; et al.	2012-11-22
Scheduling for Parallel Processing of Regionally-Constrained Placement Problem App 20120284733 - Nam; Gi-Joon ; et al.	2012-11-08
Scheduling for parallel processing of regionally-constrained placement problem Grant 8,245,173 - Nam , et al. August 14, 2	2012-08-14
Partitioning For Hardware-accelerated Functional Verification App 20120131530 - MOFFITT; MICHAEL D. ; et al.	2012-05-24
Buffer-aware Routing In Integrated Circuit Design App 20110320992 - ALPERT; Chuck ; et al.	2011-12-29
Post-placement Cell Shifting App 20110302544 - Alpert; Charles J. ; et al.	2011-12-08
Detailed Routability By Cell Placement App 20110302545 - Alpert; Charles J. ; et al.	2011-12-08
Method of minimizing early-mode violations causing minimum impact to a chip design Grant 7,996,812 - Kotecha , et al. August 9, 2	2011-08-09
Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors Grant 7,882,475 - Alpert , et al. February 1, 2	2011-02-01
Scheduling For Parallel Processing Of Regionally-constrained Placement Problem App 20100192155 - Nam; Gi-Joon ; et al.	2010-07-29
Method of Minimizing Early-mode Violations Causing Minimum Impact to a Chip Design App 20100042955 - KOTECHA; POOJA M. ; et al.	2010-02-18
Clock aware placement Grant 7,624,366 - Alpert , et al. November 24, 2	2009-11-24
System and method for sign-off timing closure of a VLSI chip Grant 7,581,201 - Kazda , et al. August 25, 2	2009-08-25
Latch placement for high performance and low power circuits Grant 7,549,137 - Alpert , et al. June 16, 2	2009-06-16
Constrained detailed placement Grant 7,467,369 - Alpert , et al. December 16, 2	2008-12-16
Method To Reduce The Wirelength Of Analytical Placement Techniques By Modulation Of Spreading Forces Vectors App 20080282213 - Alpert; Charles J. ; et al.	2008-11-13
System And Method For Sign-off Timing Closure Of A Vlsi Chip App 20080209376 - Kazda; Michael A. ; et al.	2008-08-28
Latch Placement for High Performance and Low Power Circuits App 20080148203 - Alpert; Charles J. ; et al.	2008-06-19
Constrained Detailed Placement App 20080127017 - Alpert; Charles J. ; et al.	2008-05-29
Clock Aware Placement App 20080127018 - Alpert; Charles J. ; et al.	2008-05-29
Method To Reduce The Wirelength Of Analytical Placement Techniques By Modulation Of Spreading Forces Vectors App 20080066037 - Alpert; Charles J. ; et al.	2008-03-13
System and Method of Eliminating Electrical Violations App 20070283301 - Karandikar; Arvind K. ; et al.	2007-12-06
Analytical constraint generation for cut-based global placement Grant 6,671,867 - Alpert , et al. December 30, 2	2003-12-30
Congestion mitigation with logic order preservation App 20030217338 - Holmes, Glenn E. ; et al.	2003-11-20
Analytical constraint generation for cut-based global placement App 20030196183 - Alpert, Charles J. ; et al.	2003-10-16

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