Vikhliantsev; Igor A.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Vikhliantsev; Igor A..The latest application filed is for "method and apparatus for generating memory models and timing database".
- Vikhliantsev; Igor A. - San Jose CA
- Vikhliantsev; Igor A. - Sunnyvale CA
- Vikhliantsev; Igor A. - Santa Clara CA
| Patent | Date |
|---|---|
| Method and apparatus for generating memory models and timing database Grant 8,566,769 - Andreev , et al. October 22, 2 | 2013-10-22 |
| Method and Apparatus for Generating Memory Models and Timing Database App 20120278775 - Andreev; Alexandre ; et al. | 2012-11-01 |
| Method and apparatus for generating memory models and timing database Grant 8,245,168 - Andreev , et al. August 14, 2 | 2012-08-14 |
| Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same Grant 8,151,160 - Andreev , et al. April 3, 2 | 2012-04-03 |
| Digital Gaussian noise simulator Grant 7,822,099 - Nikitin , et al. October 26, 2 | 2010-10-26 |
| Method and Apparatus for Generating Memory Models and Timing Database App 20100023904 - Andreev; Alexandre ; et al. | 2010-01-28 |
| Method and apparatus for generating memory models and timing database Grant 7,584,442 - Andreev , et al. September 1, 2 | 2009-09-01 |
| Data stream frequency reduction and/or phase shift Grant 7,313,660 - Andreev , et al. December 25, 2 | 2007-12-25 |
| Digital Gaussian Noise Simulator App 20070230621 - Nikitin; Andrey A. ; et al. | 2007-10-04 |
| Digital gaussian noise simulator Grant 7,263,470 - Nikitin , et al. August 28, 2 | 2007-08-28 |
| Method and apparatus for generating memory models and timing database App 20070136704 - Andreev; Alexandre ; et al. | 2007-06-14 |
| Process and apparatus for placing cells in an IC floorplan Grant 7,210,113 - Andreev , et al. April 24, 2 | 2007-04-24 |
| Controller architecture for memory mapping Grant 7,065,606 - Andreev , et al. June 20, 2 | 2006-06-20 |
| Method for generating tech-library for logic function Grant 7,062,726 - Andreev , et al. June 13, 2 | 2006-06-13 |
| Pseudo-random one-to-one circuit synthesis Grant 7,050,582 - Andreev , et al. May 23, 2 | 2006-05-23 |
| Process and apparatus for placement of cells in an IC during floorplan creation Grant 7,036,102 - Andreev , et al. April 25, 2 | 2006-04-25 |
| Process and apparatus for placing cells in an IC floorplan App 20050240889 - Andreev, Alexander E. ; et al. | 2005-10-27 |
| Built-in test for multiple memory circuits Grant 6,941,494 - Andreev , et al. September 6, 2 | 2005-09-06 |
| Clock tree synthesis with skew for memory devices Grant 6,941,533 - Andreev , et al. September 6, 2 | 2005-09-06 |
| Process and apparatus for placement of cells in an IC during floorplan creation App 20050091625 - Andreev, Alexander E. ; et al. | 2005-04-28 |
| Controller architecture for memory mapping App 20050055527 - Andreev, Alexander E. ; et al. | 2005-03-10 |
| Data stream frequency reduction and/or phase shift App 20050053182 - Andreev, Alexander E. ; et al. | 2005-03-10 |
| Netlist redundancy detection and global simplification Grant 6,848,094 - Andreev , et al. January 25, 2 | 2005-01-25 |
| Digital gaussian noise simulator App 20040225481 - Nikitin, Andrey A. ; et al. | 2004-11-11 |
| Method for generating tech-library for logic function App 20040221247 - Andreev, Alexandre E. ; et al. | 2004-11-04 |
| Netlist redundancy detection and global simplification App 20040128632 - Andreev, Alexander E. ; et al. | 2004-07-01 |
| Clock tree synthesis with skew for memory devices App 20040078766 - Andreev, Alexander E. ; et al. | 2004-04-22 |
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