Vijay; Dilip P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vijay; Dilip P..The latest application filed is for "method and apparatus for avoiding dicing chip-outs in integrated circuit die".

Company Profile

0.6.1

Vijay; Dilip P. - Redwood City CA
Vijay; Dilip P. - Foster City CA
Vijay; Dilip P. - Fremont CA
Vijay; Dilip P. - Blacksburg VA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for avoiding dicing chip-outs in integrated circuit die Grant 7,354,790 - Rajagopalan , et al. April 8, 2	2008-04-08
Method and apparatus for avoiding dicing chip-outs in integrated circuit die App 20060160269 - Rajagopalan; Parthasarathy ; et al.	2006-07-20
Dynamic random access memories with dielectric compositions stable to reduction Grant 6,139,780 - Desu , et al. October 31, 2	2000-10-31
Simple method of fabricating ferroelectric capacitors Grant 5,807,774 - Desu , et al. September 15, 1	1998-09-15
High temperature electrode-barriers for ferroelectric and other capacitor structures Grant 5,790,366 - Desu , et al. August 4, 1	1998-08-04
Reactive ion etching of lead zirconate titanate and ruthenium oxide thin films Grant 5,496,437 - Desu , et al. March 5, 1	1996-03-05
Method of forming multilayered electrodes for ferroelectric devices consisting of conductive layers and interlayers formed by chemical reaction Grant 5,491,102 - Desu , et al. February 13, 1	1996-02-13

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