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name:-0.011935949325562
name:-0.0050280094146729
name:-0.00040197372436523
Viero; Giorgio Patent Filings

Viero; Giorgio

Patent Applications and Registrations

Patent applications and USPTO patent grants for Viero; Giorgio.The latest application filed is for "photovoltaic module".

Company Profile
0.6.10
  • Viero; Giorgio - Stezzano IT
  • Viero; Giorgio - Stezzano BG
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Photovoltaic module
Grant 10,972,047 - Loertscher , et al. April 6, 2
2021-04-06
Photovoltaic module
Grant 10,972,048 - Loertscher , et al. April 6, 2
2021-04-06
Photovoltaic Module
App 20180248512 - Loertscher; Emanuel ;   et al.
2018-08-30
Photovoltaic Module
App 20180248511 - Loertscher; Emanuel ;   et al.
2018-08-30
Handling and positioning of metallic plated balls for socket application in ball grid array packages
Grant 7,524,698 - Viero , et al. April 28, 2
2009-04-28
Coaxial via structure for optimizing signal transmission in multiple layer electronic device carriers
Grant 7,360,308 - Oggioni , et al. April 22, 2
2008-04-22
Structure of stacked vias in multiple layer electrode device carriers
Grant 7,319,197 - Oggioni , et al. January 15, 2
2008-01-15
Power Supply Structure For High Power Circuit Packages
App 20070230150 - Castriotta; Michele ;   et al.
2007-10-04
Coaxial Via Structure For Optimizing Signal Transmission In Multiple Layer Electronic Device Carriers
App 20060288574 - Oggioni; Stefano S. ;   et al.
2006-12-28
Handling And Positioning Of Metallic Plated Balls For Socket Application In Ball Grid Array Packages
App 20060255461 - Viero; Giorgio ;   et al.
2006-11-16
Metallic Plating For Socket Applicationin Ball Grid Array Packages
App 20060196917 - Viero; Giorgio ;   et al.
2006-09-07
Coaxial via structure for optimizing signal transmission in multiple layer electronic device carriers
Grant 7,091,424 - Oggioni , et al. August 15, 2
2006-08-15
Optimized Plating Process For Multilayer Printed Circuit Boards Having Edge Connectors
App 20060008970 - Oggioni; Stefano ;   et al.
2006-01-12
Structure of stacked vias in multiple layer electronic device carriers
App 20050156319 - Oggioni, Stefano ;   et al.
2005-07-21
Optimized Conductive Lid Mounting For Integrated Circuit Chip Carriers
App 20040150097 - Gaynes, Michael A. ;   et al.
2004-08-05
Coaxial via structure for optimizing signal transmission in multiple layer electronic device carriers
App 20040069529 - Oggioni, Stefano S. ;   et al.
2004-04-15

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